Tie Cells Insertion
Here I am going to discuss about Tie Cells Insertion. Before going to
know about Tie Cells Insertion, We have to know what Tie Cells are.
Tie Cells:
Tie cells are special purpose standard cells whose output is Constant
High or Constant Low. These cells are used to hold (tie) the input of other
cells which are required to be connected Constant High (Vdd) or Constant Low
(Vss) values.
Tie High Cell:
Tie High Cell is special purpose standard cell whose output is Constant
High (Vdd).
Tie Low Cell:
Tie Low Cell is special purpose standard cell whose output is Constant
Low (Vss).
There are some unused inputs in the
design netlist. These unused inputs should not be floated. They should be tied
to either Power (Vdd) or Ground (Vss). The inputs which are required to connect
Vdd, connect to Tie High cells. The inputs which are required to connect Vss,
connect to Tie Low cells. This is the purpose of Tie cells in the design
Why Tie cells are inserted?
In lower technology nodes the gate
oxide of the transistor is so thin and sensitive to voltage fluctuations in the
power supply. If the gate of the transistor is directly connected to the
Power/Ground network (Power Grid Network), the gate oxide of the transistor
might be damaged due to voltage fluctuations in the power supply. To overcome
this disadvantage, Tie cells are inserted.
To perform Placement Optimization
or Physical optimization, Automatic Insertion and Optimization of Tie offs are
required in the design. The following commands are used to execute the same.
set_auto_disable_drc_nets
-constant false
set
physopt_new_fix_constants true
set_attribute [...]
max_fanout 12
set_attribute [...] max_capacitance 0.2
-type float
Tie-off Optimization:
Tie cells optimization means using
a tie cell to hold (tie) as many inputs as possible at given logic level, while
meeting specified maximum Fanout and maximum capacitance constraints (Logical
DRCs).
The set_auto_disable_drc_nets command enables DRC on constant nets.
The set physopt_new_fix_constants
variable to true causes placement tool
to observe the maximum capacitance constraint during tie-off optimization.
The
maximum capacitance constraint is determined by the max_capacitance attribute,
which can be set with the set_max_capacitance or set_attribute command.
The set_attribute command can be used to specify explicitly both
the maximum fanout and maximum capacitance constraints for objects in the
design.
Note: We can also insert tie cells manually with the
command connect_tie_cells. The
command inserts tie cells and connects them to specified cell ports, while
meeting maximum fanout and maximum wire length specified in the command.