Thursday, 28 March 2013

Static Timing Analysis (STA) Interview Questions

Static Timing Analysis Interview Questions

Static Timing Analysis plays major role in physical design(PD) flow. It checks the design whether it is working properly at specified operating frequency by checking the  Timing Constraints predefined by vendor tool are meeting by the all timing paths across design. Here I am sharing very basic level interview questions on Static Timing Analysis. you can find the elaborate explanations in further posts.


1. What is Static Timing Analysis(STA)?
A. Static timing analysis is a method for determining if a circuit meets timing constraints without having to simulate. So, it validates the design for desired frequency of operation, without checking the functionality of the design.
2. What is Setup Time?
A. Setup time is the amount of time before the clock edge that the input signal needs to stable to guarantee it is properly accepted on the clockedge.
3. What is Holdtime?
A. Hold time is the amount of time after the clock edge that the input  should be stable to guarantee it is properly accepted on the clock edge.
4. what is setup and Hold time violations?
A. Voilating above setup and hold time requirements is called setup and hold time violations. If there is setup and hold time violations in the design does not meet the timing requirements and the  functionality of the design is not reliable. STA checks this setup and hold violations.
5. How can you avoid setup time violations?
A.  1. Play with clock (Useful) skew.
      2. Redesign the flipflops to get lesser setup time
      3. The combo logic between flipflops should be optimized to get minimum delay
     4. Tweak launch flip-flop to have better slew at the clock pin, this will make launch flip-flop to be fast there by helping fixing setup violations.
6. How can you avoid hold time violations?
A. 1. By adding delays using buffers
     2. By adding lockup-latches
 7. What is Slack?
 A. The difference between Required Arrival Time and Actual Arrival Time is called as Slack. The amount of time by which a violation (Either setup or Hold) is avoided is called the slack.




  8. What is Negative slack?
 A. The difference between required arrival time and actual arrival time is Negative, then it is called as                 Negative slack. If there is negative slack, the design is not meeting the timing requirements and the paths        which have negative slack called as violating paths. We have to fix these violations to make the design            meeting timing.

 9. What is Positive slack ?
A. The difference between required arrival time and actual arrival time is positive, then is called as positive          slack. If there is positive slack, The design is meeting the timing requirements and still it can be                improved.
10. In back-end design which violation has more priority? Why?
 A. In back-end design, Hold violation has more priority than Setup Violation. Because hold violation is              related to data path and not depends on clock. Setup violation can be eliminated by slowing down the          clock (Increasing time period of the clock). 

7 comments:

  1. 10. Tsetup = Tclk- {T(clk-q) + T comb}
    Thold = T(clk-q) + T comb
    So setup violation can be fixed by reducing frequency and your chip wil work but if your chip is having hold violation, through it away :)

    ReplyDelete
    Replies
    1. Yes, you are right Neelesh. That's why Hold violation should be eliminated.

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    2. even though the design is having hold violations we can use that design. but the hold violations should be of 10ps.

      Delete
  2. It's all about timing when it comes to best performing Chip design !!

    https://www.udemy.com/vlsi-academy-sta-checks/?couponCode=new_course_v2

    ReplyDelete
  3. What's the difference between SDP (structured data path) and traditional placement flow ?

    ReplyDelete