Friday, 2 August 2013

Low Power Design

Power Planning:

Power is limiting factor affection performance and features in most important products. When you decided to buy a mobile, What are the features you look for? The mobile should have camera (primary or secondary), 3G/4G support, and all the features. Apart from these features, The mobile should be light weight(portable), long battery life. For suppose you have to travel long distance, you are carrying your mobile. If the battery of mobile lasts in few hours. Then you hate to charge the battery again and again. To make battery lasts for long time, Low power design comes into the picture. Power management issues are affecting every aspect of of the design. They can be
  • Architecture
  • Design Techniques
  • Process Technology
  • Design methodology
  • Software
Challenges of Low Power:
  • Lowering Supply Voltage
  • Increasing Device Densities as Technology Node Shrinking
  • Increasing Clock Frequencies
  • Lowering Transistor Threshold Voltage

Components of Power:
  • Static Power
  • Dynamic Power
  • Total Power Consumption
Total Power consumption = Static power consumption + Dynamic Power Consumption


1. Dynamic Power:


  • During the switching of Transistors
  • Depends upon the clock frequency and switching activity 
  • Consisting of switching and internal power
  • Dynamic power consumption is given by
So Dynamic power depends on the Load capacitance, Clock frequency and operating voltage.

Dynamic power can be reduced by lowering operating voltage (Vdd), lowering switching activity and lowering switch capacitance (C load).

Load capacitance (C load) depends on 
  1. Output node capacitance of the logic gate (Due to the drain diffusion region)
  2. Total interconnects and capacitance ( Has higher effects as technology node shrinks)
  3. Input node capacitance of the driven gate ( Due to gate oxide capacitance)
Internal Power:
 Power consumed by the cell when input changes, but the output doesn't change. Lower threshold voltages and slower transitions result in more internal power consumption.

Short Circuit Power:
For finite rise and fall time, When Vtn < Vin < (Vdd-Vtp) holds, there will be a conductive path open between Vdd and GND because both the nMOS and pMOS devices will be simultaneously on. 

Short-circuit power is typically estimated as:


This short circuit power component is usually not significant in logic design, but it appears in transistors that are used to drive large capacitances, such as bus wires and especially off-chip circuitry. As wires on chip became narrower, long wires became more resistive. CMOS gates at the end of those resistive wires see slow input transitions.

To minimize the total average short circuit current, it is desirable to have equal input and output edge times. In this case, the power consumed by the short circuit current is typically less than 10% of the total dynamic power. An important point to note is that if the supply is lowered to below the sum of the thresholds of the transistors, Vdd<Vthn+|Vthp|, the short circuit currents can be eliminated because both devices will never be on at the same time for any input voltage value.By balancing transistor size we can get equal Rise time and fall time. 


2. Static Power:
  • Transistor leakage current that flows whenever power is applied to the device
  • Independent of the clock frequency and switching activity
  • Static power is given by

Static Power can be reduced by lowering operating voltage and using fewer leaking transistors.

Leakage Power :

The power consumed by the sub threshold currents and by reverse biased diodes in a CMOS transistor is considered as leakage power. The leakage power of a CMOS logic gate does not depend on input transition or load capacitance and hence it remains constant for a logic cell.

There are different low power design techniques to reduce the above power components
     
Dynamic power component can be reduced by the following techniques                     
               1. Clock gating
               2. Voltage and Frequency Scaling (DVFS, SVFS)
               3. Gate Sizing
               4. Multi Vdd
               
Static (Leakage) power component can be reduced by the following techniques 

               1. Multi Vt
               2. Power Gating
               3. Use new devices like Finfet and SOI
               4. Back (Substrate) Bias

We will discuss about these techniques in our next blogs in detail. Now Android Application available, Click here to download it


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