Thursday, 20 February 2014

Physical Design Flow – Practical Approach with IC Compiler (Synopsys)

Physical Design Flow – Practical Approach with IC Compiler (Synopsys)


The general ICC flow is as shown in figure 1. The first step in ICC Flow is Data Setup. In this step, we create “Container” which is known as “Design Library”.  The inputs which are required for physical design are loaded into this Design Library.  i.e., The Design Library contains Logical/Timing Library files, Physical Library Directories, Constraints, Gate-level Netlist, Technology File, RC (TLU+) Model Files. We provide these Design Library as input to the IC Compiler. The output of the IC Compiler will be Placed, Routed and Optimized layout with Clock Trees as shown in below figure 2.

Inputs for ICC Physical Design Flow:
As shown in figure 2 the inputs for ICC Physical Design flow are logical/Timing libraries, Physical libraries, Technology file, Design Constraints, Gate Level Netlist, RC (TLU+) Model Files. These are given to the ICC tool. Here I am going to discuss about these inputs.

                                                             Figure 2 Inputs and Outputs of ICC Flow

1. Logical/Timing Libraries (.db):
Logical Libraries are library files which provide timing and functionality information of each and every standard cells (AND, OR, Flipflops etc) used in the design. It also provides timing information of hard macros such as IP, ROM, RAM etc. Logical Libraries define and load the Logical DRC such as Maximum fanout, Maximum Transistion, Min/Max Capacitances. Logical libraries are also used at Synthesis step in DC. These are in .db form. Logical libraries are specified by the variables target_library and link_library.

2. Physical/Reference Libraries (Milkyway .db):
Physical/Reference libraries contain Physical Information of standard, macro and pad cells, which is necessary for placement and routing. These libraries define placement tile (Height of placement rows, minimum width resolution, preferred routing direction, Pitch of routing tracks etc). These libraries are specified with command create_mw_lib –mw_reference_library. 


3. Technology file:
A Technology file is provided by the technology vendor. Technology file is unique for each technology. Technology file contains the information related to metal/via information such as
·         Units and precision for electrical units (Voltage,  Current, Power etc)
·         Define colors and patterns of layers for display
·         Number and Name designations for each metal/via
·         Physical and Electrical characteristics of each metal/via
·         Define Design rules such as minimum wire  widths and minimum wire to wire spacing 
·         Contains ERC rules, Extraction Rules, LVS rules
·         Provide parameterized cells (PCELLs) for MOS, caps etc
·         Create menus and commands (Ex: create contact)
4. RC (TLU+) Model:

ICC calculates delay for every net and every cell. To calculate delay tool needs each net R’s and Capacitances. IC Compiler calculates interconnect R and C values using net geometry and TLU+ look up tables. It models UDSM process effects. TLU+ is a binary table which has R and C values for delay calculation.

5. Netlist:
It can be in the form of Verilog or VHDL(.v or,vhdl). This netlist is produced during logical synthesis, which takes place prior to the physical design stage.
6. Constraints:
Design constraints (like system clock definition and clock delays, Multiple cycle paths, Input and output delays, Minimum and maximum path delays, Input transition and output load capacitance, False paths) are identical to those which were used during the front-end logic synthesis stage prior to physical design. It is available in the form of SDC (Synopsys Design Constraints).  

1 comment:

  1. Could you please explain about filler cells utilization ? I was confused about power rail continuity and nwell/pwell continuity requirement. I think that power rails are located on Metal layer 1 and layer 2, thus it is is always continuous, isn't ?

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