Saturday, 6 February 2016

Tuesday, 19 January 2016

Sanity Checks in Physical Design Flow

 Sanity Checks in Physical Design Flow
  • check_library
  • check_timing 
  • report_constraint 
  • report_timing 
  • report_qor
  • check_design

check_library validates the libraries i.e., it performs consistency checks between logical and physical libraries, across logical libraries, and within physical libraries.

This command checks library qualities in three main areas:
Physical library quality
Logic versus physical library consistency
Logic versus logic library consistency

PNR tool wont optimize the paths which are not constrained. So we have to check any unconstrained paths are exist in the design. check_timing command reports unconstrained paths.
If there are any unconstrained paths in the design, run the report_timing_requirements command to verify that the unconstrained paths are false paths.

It reports to check the following parameters. 
Worst Negative Slack (WNS)
Total Negative Slack (TNS)
Design Rule Constraint Violations

report_timing displays timing information about a design.
The report_timing command provides a report of timing  information  for the  current design.  By default, the report_timing command reports the single worst setup path in each clock group.

report_qor displays QoR information and statistics for the current design. This  command  reports timing-path group and cell count details, along with current design statistics such as combinational, noncombinational, and  total  area. 
The  command also reports static power, design rule violations, and compile-time details.

check_design checks the current design for consistency.

The check_design command checks the internal representation of the current design for consistency, and issues error and warning  messages  as appropriate.

Error messages indicate design problems of such severity that the compile command does not accept the design
Warning messages are informational and do not necessarily indicate design  problems.  However, these messages should be investigated.

Potential  problems  detected  by  this  command include

  • Unloaded input ports or undriven output ports 
  • Nets without loads or drivers  or  with multiple  drivers 
  • Cells  or  designs  without inputs or outputs 
  • Mismatched pin counts between an  instance  and  its  reference 
  • Tristate buses with non-tristate drivers 
  • wire loops across hierarchies, and so forth.

Wednesday, 30 April 2014

Tie Cells Insertion

Tie Cells Insertion

Here I am going to discuss about Tie Cells Insertion. Before going to know about Tie Cells Insertion, We have to know what Tie Cells are. 

Tie Cells:
Tie cells are special purpose standard cells whose output is Constant High or Constant Low. These cells are used to hold (tie) the input of other cells which are required to be connected Constant High (Vdd) or Constant Low (Vss) values.

Tie High Cell:
Tie High Cell is special purpose standard cell whose output is Constant High (Vdd).

Tie Low Cell:
Tie Low Cell is special purpose standard cell whose output is Constant Low (Vss).

There are some unused inputs in the design netlist. These unused inputs should not be floated. They should be tied to either Power (Vdd) or Ground (Vss). The inputs which are required to connect Vdd, connect to Tie High cells. The inputs which are required to connect Vss, connect to Tie Low cells. This is the purpose of Tie cells in the design

Why Tie cells are inserted?
In lower technology nodes the gate oxide of the transistor is so thin and sensitive to voltage fluctuations in the power supply. If the gate of the transistor is directly connected to the Power/Ground network (Power Grid Network), the gate oxide of the transistor might be damaged due to voltage fluctuations in the power supply. To overcome this disadvantage, Tie cells are inserted.

To perform Placement Optimization or Physical optimization, Automatic Insertion and Optimization of Tie offs are required in the design. The following commands are used to execute the same.

set_auto_disable_drc_nets -constant false
set physopt_new_fix_constants true
set_attribute [...] max_fanout 12
set_attribute [...] max_capacitance 0.2 -type float

Tie-off Optimization:
Tie cells optimization means using a tie cell to hold (tie) as many inputs as possible at given logic level, while meeting specified maximum Fanout and maximum capacitance constraints (Logical DRCs). 

The set_auto_disable_drc_nets command enables DRC on constant nets.

The set physopt_new_fix_constants variable to true causes placement tool to observe the maximum capacitance constraint during tie-off optimization.

The maximum capacitance constraint is determined by the max_capacitance attribute, which can be set with the set_max_capacitance or set_attribute command. The set_attribute command can be used to specify explicitly both the maximum fanout and maximum capacitance constraints for objects in the design.

Note: We can also insert tie cells manually with the command connect_tie_cells. The command inserts tie cells and connects them to specified cell ports, while meeting maximum fanout and maximum wire length specified in the command.

Wednesday, 2 April 2014

Congestion in VLSI Physical Design FLow

Congestion in VLSI Physical Design Flow

Here let us discuss about congestion. What is Congestion? What are the reasons for Congestion? How congestion can be fixed?

What is Congestion?
If the number of routing tracks available for routing in one particular area is less than the required routing tracks then the area said to be congested. There will be a limit for number of nets that can be routed through particular area.

What are the reasons for Congestion?
  • High Standard cell density in small area
  • Placement of standard cells near macros
  • High pin density at the edge of macro
  • Bad floorplan
  • During IO optimization tool does buffering, So lot of cells placed in the core area
How congestion can be Analysed?
Congestion can be analysed by using congestion map as shown below figure.

  • If the congestion is not too severe, The actual route can be detoured around congested area. The detoured nets will have worse RC delays than actual VR estimates.
  • If the congestion is too severe, the design can be un-routable. This is really not good. It is important to minimize or eliminate the congestion before continuing.

How to fix Congestion?
  • Rerun the fast placement with Congestion driven option (Congestion driven placement)
  • Modify physical constraints such as adjust cell density in congested areas. Because higher cell density cause for congestion. 
  • Use/Modify proper blockages. i.e., Soft blockages, Hard blockages, Macro Padding are used proper locations to minimize the congestion near macros.
  • Modify floorplaning such as moving macros, change core shape/size, Move pins to give enough room for routing
What happens during congestion driven placement?
As discussed earlier, Congestion driven placement is performed to reduce the congestion. During congestion driven placement, the cells (Higher cell density) which caused for congestion are spread apart. If the cells along timing critical paths are spread apart to minimize congestion, What happens? 

If the cells along timing critical paths spread apart, the timing constraints along that particular paths are not met which cause for timing violations. But these violations can be fixed during incremental optimization. 

What are the care should be taken using congestion driven option?
  • If there is some congestion, use medium effort option
  • If the congestion is bad, use high effort option
  • If there is no congestion, Don't use congestion driven option. If we use congestion driven option in this case, It takes more rum time for placement.
How modify physical constraints reduce congestion?
As discussed earlier, Higher cell density can cause for congestion. By default the cell density can be upto 95%. We can reduce the cell density at congested areas by using coordinate option.
As shown in below figure, we can set cell density to a flexible number to reduce the congestion by using the command 
set_congestion_options - max_util 0.6\
                                        - coordinate {x1 y1 x2 y2}

Here we set the maximum cell density  upto 60% and given the coordinates for the particular area.

How blockages and macro padding(Halos) reduce congestion?
 By using blockages and halos, They prevent the tool placing cells in that particular locations to give enough space for routing near the macros. For more details, please refer Blockages halos post.

Soft Blockages created only for the channels between macros (or) Between macro & the core boundary to give enough space for routing.

Hard blockages always created on the four sides of macro for not to place standard cells or macros near to the macro.
Macro Padding: If the design contains macros that are not placed near another macro (or) the edge of the core then macro padding(Halo) is created. Standard cells cant be placed in this region which give more routing resources to the signal routes.

Synopsys IC Compiler manual

Thursday, 27 March 2014

High Fanout Net Synthesis (HFNS)

High Fan-out Net Synthesis

Before going to discuss about we have to know the basic terminology like What is Fanout? What are High Fanout Nets (HFN)? Why we are going for High Fanout Net Synthesis (HFNS)?

What is fanout?
Fanout is the number of gate inputs to which the output can be safely connected. i.e., The load that a gate output can drive. The maximum fanout of an output measures it's load-driving capability. Fanout belongs to the output.

What are High Fanout Nets(HFN) ?
High Fanout Nets are the nets which drive more number of load. We set some max fanout limit by using the command set_max_fanout. The nets which have greater than these limit are considered as High Fanout Nets (HFN). Generally clock nets, reset, scan, enable nets are High Fanout Nets.

What is High Fanout Net Synthesis (HFNS)?
High Fanout Net Synthesis (HFNS) is the process of buffering the High Fanout Nets to balance the load.

To balance the load HFNS is perfomed. Too many load affects delay numbers and transition times. Because load is directly proportional to  the delay. By buffering the HFN the load can be balanced. This is called as High Fanout Net Synthesis(HFNS).

Where HFNS ?
Generally at placement step HFNS performed. HFNS can also be performed at synthesis step using Design Compiler. But it's not good idea, Buffers will be removed during PD and again HFNS is performed. It's very time consuming process. So HFNS at synthesis step is not recommended. HFNS at synthesis step gives an idea whether HFN are present in data path or not. Generally HFN are present in clock paths, rest, enable and  scan paths. 

Care that should taken during HFNS:
1. Make sure an appropriate fanout limit is set using set_max_fanout command
2. Verify the SDC used for PD should not have set_ideal_network or set_dont_touch commands on High      Fanout Nets.
3. Use ideal clock network - As clock nets are synthesized separately during Clock Tree Synthesis (CTS)          step, we set clock network as ideal network.


As clock nets are considered as ideal, buffering is not performed on the clock nets even they are High Fanout Nets. So, HFNS is the process of synthesizing other than clock nets, such as reset, scan, test enable nets is called as High Fanout Net Synthesis (HFNS) 

Sunday, 23 February 2014

Different cells used for Low Power Design - Power management Techniques

Level Shifters, Isolation Cells, Retention Registers, Power Switches, Always on Cells 

Level Shifters:

Level Shifters are used in multi voltage design in which more than one voltage supply used. Consider In your design two voltage domains are there. One voltage domain V1 has 1.2V power supply another domain V2 has 1V power supply. Signal has to cross from one domain to another domain while in functional mode. Now assume signal crossing from Low voltage domain V2 to High voltage domain V1, It's logic is interpreted wrongly at V1. To prevent this level shifters are inserted between the different voltage domains for the signals which cross from low voltage domain to High voltage domain and from High voltage domain to low voltage domains.

The main functionality of the level shifters is to shift the voltage one voltage to another voltage level depending upon the the signal crossing different voltage domains.

Isolation Cells:

Isolation cells are used between the domains. Consider there are two domains are in your design i.e,. D1 and D2. The domain D1 is power shut down mode and other domain D2 is in active mode. Since Domain D1 is power down mode it can propagate invalid logic to domain D2. To prevent this, Isolation cells are inserted between the domains to clamp a known value at its output, While domain D1 is shut down mode. Isolation cells should be placed in always on domain to serve it's functionality (clamp the known value to the other domain)

Power Switches:

Power switches are used in power gating technique. As we already discussed in previous post, Power gating is used to reduce the static (Leakage) power in the design. Power gating is performed by shutting down the power for portion of design. Power switches are used to turn off the portions of design which are inactive at a point of time to reduce leakage power.

Retention Registers:

Retention Registers are used to store register states before power down mode. These values will be restored when power is up. So retention cells should be always on to serve the purpose. As these are always on, It can consume power even power down mode. 

Always On cells:

These cells are special cells which should be always on to their purpose.

Thursday, 20 February 2014

Physical Design Flow – Practical Approach with IC Compiler (Synopsys)

Physical Design Flow – Practical Approach with IC Compiler (Synopsys)

The general ICC flow is as shown in figure 1. The first step in ICC Flow is Data Setup. In this step, we create “Container” which is known as “Design Library”.  The inputs which are required for physical design are loaded into this Design Library.  i.e., The Design Library contains Logical/Timing Library files, Physical Library Directories, Constraints, Gate-level Netlist, Technology File, RC (TLU+) Model Files. We provide these Design Library as input to the IC Compiler. The output of the IC Compiler will be Placed, Routed and Optimized layout with Clock Trees as shown in below figure 2.

Inputs for ICC Physical Design Flow:
As shown in figure 2 the inputs for ICC Physical Design flow are logical/Timing libraries, Physical libraries, Technology file, Design Constraints, Gate Level Netlist, RC (TLU+) Model Files. These are given to the ICC tool. Here I am going to discuss about these inputs.

                                                             Figure 2 Inputs and Outputs of ICC Flow

1. Logical/Timing Libraries (.db):
Logical Libraries are library files which provide timing and functionality information of each and every standard cells (AND, OR, Flipflops etc) used in the design. It also provides timing information of hard macros such as IP, ROM, RAM etc. Logical Libraries define and load the Logical DRC such as Maximum fanout, Maximum Transistion, Min/Max Capacitances. Logical libraries are also used at Synthesis step in DC. These are in .db form. Logical libraries are specified by the variables target_library and link_library.

2. Physical/Reference Libraries (Milkyway .db):
Physical/Reference libraries contain Physical Information of standard, macro and pad cells, which is necessary for placement and routing. These libraries define placement tile (Height of placement rows, minimum width resolution, preferred routing direction, Pitch of routing tracks etc). These libraries are specified with command create_mw_lib –mw_reference_library. 

3. Technology file:
A Technology file is provided by the technology vendor. Technology file is unique for each technology. Technology file contains the information related to metal/via information such as
·         Units and precision for electrical units (Voltage,  Current, Power etc)
·         Define colors and patterns of layers for display
·         Number and Name designations for each metal/via
·         Physical and Electrical characteristics of each metal/via
·         Define Design rules such as minimum wire  widths and minimum wire to wire spacing 
·         Contains ERC rules, Extraction Rules, LVS rules
·         Provide parameterized cells (PCELLs) for MOS, caps etc
·         Create menus and commands (Ex: create contact)
4. RC (TLU+) Model:

ICC calculates delay for every net and every cell. To calculate delay tool needs each net R’s and Capacitances. IC Compiler calculates interconnect R and C values using net geometry and TLU+ look up tables. It models UDSM process effects. TLU+ is a binary table which has R and C values for delay calculation.

5. Netlist:
It can be in the form of Verilog or VHDL(.v or,vhdl). This netlist is produced during logical synthesis, which takes place prior to the physical design stage.
6. Constraints:
Design constraints (like system clock definition and clock delays, Multiple cycle paths, Input and output delays, Minimum and maximum path delays, Input transition and output load capacitance, False paths) are identical to those which were used during the front-end logic synthesis stage prior to physical design. It is available in the form of SDC (Synopsys Design Constraints).  

Sunday, 15 December 2013

VLSI Companies (Product Based) in India

VLSI Companies in India

1. Intel (Intel Technology India Pvt Ltd)
    136 Airport Road, Bangalore, Karnataka, India
    Unit 03, No 65/2 Bagmane Tech, Byrasandra in Ward no. 83, Bangalore, Karnataka, India
    4 Floor, Block B, Brigade Tech, Pattandur Agrah Villg Whitefld, Bangalore, Karnataka, India
    ITPL Rd, Site 6/2 & 6/3, 4Flr, A/B Wing Thoobarahalli Village, Bangalore, Karnataka, India
    Discover Bldg, Unit 1, 10/Fl, Int'l Tech Park, Whitefield Rd, Bangalore, Karnataka, India
    Inventor Bldg, Unit 1& 2, 5/Fl, Int'l Tech Park, Whitefield Rd, Bangalore, Karnataka, India
    Navigator Bldg, Unit 1&2, 7/Fl, Int'l Tech Park, Whitefield Rd, Bangalore, Karnataka, India
    Innovator Bldg, 1/Fl, Int'l Tech Park, Whitefield Rd, Bangalore, Karnataka, India
    Devarabisanahalli Village, Sarjapur Ring Road, Bangalore, Karnataka, India
    3rd Flr Tower A, Plot C28 & 29, Sector 62, Noida, Uttar Pradesh, India

Phone : 080-22869330.   FAX : 080-22867431
Area : Microprocessors, Network Processors, DSP Processors, Switching, Embedded Processors.
Skill : VHDL/Verilog, VLSI Design, ASIC Design, Architecture, Testing/DFT/BIST.

2. Qualcomm
Adarsh Eco Place, 176, EPIP Zone, Phase II, Whitefield, Kundalahalli Hobli, KR Puram Taluk,               Bangalore, Karnataka 560066, India.
Plot Nos 125-127, EPIP, Phase II, Whitefield, Bangalore, Karnataka 560066, India.
Plot No131, Sonnenahalli Village, EPIP Phase II, Whitefield, Bangalore, Karnataka 560066, India.
Building No 2 B, 9th Floor, Maximus Towers, Mindspace Complex, Hyderabad, AP 500081, India.
Building No8, Floors 1,3,4,5, Mindspace, Hitec City Road, Madhapur, Hyderabad, AP 500081, India.

Area : CDMA Wireless Communications, 3G Chip Sets, Library Development.
Skill : VLSI Design, ASIC Design, DSP Architectures, Physical Design, DFT, Verification, VHDL/Verilog.

3. Brodcomm
Campus 3A, 5th Floor,
RMZ Eco Space,
Bellandur Village,
Varthur Hobli,
BANGALORE -- 560 037. 
Phone : 080-51484444.   FAX : 080-51539999.
Area : Communications, VoIP, Multimedia, Consumer.
Skill : VLSI Design, Architectures, VHDL/Verilog, Analog Design, DFT, Physical Design.

4. Nvidia

Brigade South Parade,
10, MG Road,
BANGALORE -- 560 001. 
Phone : 080-56948400.   FAX : 080-56610980. 

Level 1-4, Muttha Chambers,
Senapati Bapat Road,
PUNE -- 411 016. 
Phone : 020-56413000.   FAX : 020-56022744.
Area : Graphics, Media Processors.
Skill : VHDL/Verilog, ASIC Design, VLSI Design, Architectures, Computer Arithmetic.

5. LSI
Global Technology Park, Block-C, Marathahalli Outer Ring Road, Devarabeesanahalli, Bangalore 560 103, Karnataka, India
Phone: +91-80-4197 8700 Fax: +91-80-4197 8701

3rd and 4th Floor, Building #4, Commerzone, Survey, 144,145, Samrat Ashok Path, Off Airport Road, Yerwada, Pune, Maharashtra, India 411 006
Phone: +91-020-40104700 Fax: +91-020-40104701

6. ST Micro Electronics
India Design Centre,
Plot no. 1, Knowledge Park III,
GREATER NOIDA -- 201 308. 
Phone : 0120-2352999.   FAX : 0120-2569497.
Area : Consumer, Memory, Standard Products, Technology Library, Peripherals, Industrial Control, Imaging, Multimedia. 
Skill : Analog, Mixed-signal, Physical Design, VHDL/Verilog, Architectures, DFT, Formal Verification, Scripting.

7. Texas Instruments
Bagmane Tech Park,
C. V. Raman Nagar, 
Bangalore 560 093. 
Phone : 080-25345454, 25345455.   FAX : 080-25048213.
Area : DSP Processors, Memory, PCI, 3G Wireless.
Skill : VHDL/Verilog, VLSI Design, CAD Tools, RF Design.

8. ST Ericssion

Street address:Ericsson Forum DLF Cyberciti Extended address:Sector-25A Locality:Gurgaon Haryana Postal code:122 002 Country:India 
Phone:+91 124 4151201 Phone:+91 124 4151001 Fax:+91 124 2565454

9. AMD (Advanced Micro Devices)
AMD India Pvt Ltd.
#102-103, Export promotion Industrial Park,
Whitefield, Bangalore-560066
Karnataka, India
Tel: +91-80-332-30000

AMD Research & Development Ctr. India Private Limited 
Mindspace - Cyberabad
APIIC Software Layout,
8th-11th Floor,
Building No: 11, 
Madhapur, Hyderabad
Andhra Pradesh-500081 India
Tel: +91 40 3061 5000

10. ARM
Level III, Salarpuria Touchstone
Marthahalli-Sarajapur Outer Ring Road,
Varthur Hobli, 
Bangalore-560 103 
Contact Details
Tel. +91 80 2518 5000   Fax +91 80 2844 0914

Will be continued......

Saturday, 14 December 2013

IR Drop Analysis Interview Questions

IR Drop Analysis Interview Questions

1. What is IR Drop Analysis? 
A. The power supply in the chip is distributed uniformly through metal layers (Vdd and Vss) across the              design. These metal layers have finite amount of resistance. When voltage is applied to this metal wires          current start flowing through the metal layers and some voltage is  dropped due to that resistance of metal      wires and current. This Drop is called as IR Drop.
     For example, a design needs to operate at 2 volts and has a tolerance of 0.4 volts on either side, we need      to ensure that the voltage across its power pin (Vdd) and ground pin (Vss) in that design does not fall            short of 1.6 Volts.The acceptable IR drop in this context is 0.4 volts. That means the design in this                context can allow upto 0.4 volts drop which does not effect the timing and functionality of design. The            process of analyzing this IR Drop is called IR Drop Analysis. 

2. What are the different types of IR Drop Analysis?
A. There are two types of IR Drop Analysis        
           1. Static IR Drop Analysis
           2. Dynamic IR Drop Analysis
      Static IR drop Analysis is vectorless power analysis with average current cycles, whereas, Dynamic IR         drop analysis is vector based power analysis with worst-case switching currents.

3. What are the different tools used for IR Drop Analysis?
A. Various tools are available for IR Drop Analysis. Voltagestorm from Cadence, Redhawk from Apache           are mainly used to show IR Drop on chip.

4. What are the different reasons for high voltage drop in a design?
A. In a design if there is high static or dynamic voltage drop, It could be due to one of the following reasons.

  1. High current flowing through the power grid : can affect Static as well as Dynamic IR drop
  2. High PG grid impedance : can affect static as well as Dynamic IR Drop
  3. Simultaneous Switching : can affect only Dynamic
  4. Insufficient number of voltage sources : can affect Static as well as Dynamic Drop
  5. High Package parasitics : can affect Static as well as Dynamic Drop
  6. Inadequate amount of Decaps available : Can affect only Dynamic
5. How to find the high IR Drop analysis is due to high current flowing through the power (PG) grid?
A. IR Drop is Signal Integrity(SI) effect caused by wire (metal) resistance and current drawn off from Power     (Vdd) and Ground (Vss) grids. Static or Dynamic IR Drop is proportional to the current flowing through       the power grid. High average current can cause for high Static IR Drop. Similarly in dynamic analysis,           high transient(switching) current can lead to high Dynamic IR drop.
  Average current is proportional to the average power of the design. High average power can affect both
  static and dynamic voltage drop results. Redhawk power summary report file (adsRpt/power_summary.rpt)   will give you the details of power consumption of the design. Power summary report will give you the             power consumption for each voltage domain, frequency domain and for each cell type in the design.

 Instance power file (adsRpt/<design>.power.rpt) will contain instance specific power values. You
 can also click on any instance in the GUI to get more details of power calculation for that instance.
 In Redhawk GUI, you can see the sorted list of high power instances in the design using “Results
 -> List of Highest Power Instances for Static Simulation” menu.
                                  Figure1. Redhawk Power Summary Report (Source : Apache Redhawk Manual)

You can use the Power Density map (PD) (in figure2) to get the power density distribution in the design. Similarly, Instance power map (IPM) will show you the instance power distribution. Similarly, clock power map (CPM) will show power distribution separately for clock related instances in the design.

                                            Figure2. Redhawk Home page GUI (Source : Apache Redhawk Tool)

Average power has both static and dynamic components. Static component is the leakage power.
  • You can look at the leakage power map (LPM) in the results panel (figure2) to see whether there are any cells with excessive leakage. 
  • From the instance power file (adsRpt/<design>.power.rpt) you can find leakage power component for any instance.
                                 Figure3. Power Density Map (Source : Apache Redhawk Manual)

Dynamic component is contributed by internal power and the switching power. This component is
proportional to the frequency, load and toggle rate. Reason for high dynamic power could be one
of the following:
  • High frequency of switching.
  • High Load capacitance.
  • High toggle rate or BLOCK_POWER_FOR_SCALING used in the analysis.
From the instance power file, you can get the of the power calculation.
  • You can analyze the Instance Frequency Map (IFM) to see whether high frequency is causing high power in some region.
  • Load Cap map (LC) will tell you whether high load is causing the dynamic component of power. High load issue normally happens when you have un-synthesized clock tree or scan chains, with some buffers driving huge fanout load.
  • High toggle rate can also cause high dynamic power. Redhawk derives the toggle rate from one of the following ways.
  • User can scale the power values computed by scaling the TOGGLE_RATE using the
  • GSR keyword BLOCK_POWER_FOR_SCALING. Values specified in this section directly affect your static and dynamic results. 
You can also click on any metal / via segments to see the amount of current flowing through the geometry. Static analysis shows the average current and dynamic analysis shows peak current. In static analysis, it will also show you the current direction. “CUR” Map shows the current distribution throughout the chip.High transient current can be caused by simultaneous switching in the design.

6. How to find the high IR Drop analysis is due to high PG impedance?
A. High Power grid resistance will impede the current flow in the power grid causing high static or dynamic voltage drop. You can use PG Resistance Map (View -> Resistance Maps) to highlight areas with high PG resistance. Also, you can write out the PG Resistance report using the Redhawk command “perform gridcheck”. More details on PG Weakness analysis can be found in the application note “Analyzing PG Weakness Results in Redhawk GUI”.

Redhawk has several features to analyze the structural weakness issues in the power grid. You
can use “View -> Connectivity” menu to analyze PG structural issues such as:
  • Disconnected instances
  • Disconnected wires/vias
  • Shorts
  • Missing vias
                                            Figure4. Connectivity Analysis (Source : Apache Redhawk manual)

When you highlight disconnected instances in Redhawk GUI, instances with VSS disconnect will get highlighted in Blue, VDD disconnect will get highlighted in Green and both VDD/VSS disconnect will get highlighted in Yellow. Corresponding text reports are also available inside adsRpt directory (adsRpt/*.unconnect, adsRpt/apache.missingVias etc).

If there is any major disconnect in the power grid, it will affect the current flow in the design. You can use the current map (CUR button) to review the current flow through the power grid to see whether there are any surprises.

If you are performing RLC extraction on the power grid, high inductance can also cause high dynamic drop. You can perform a dynamic analysis based on RC extraction and compare the results to see whether L component is causing the high drop.

1. Redhawk User's Manual by Apache Design Analysis

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Friday, 18 October 2013

IR Drop Analysis using Redhawk - Overview

IR Drop Analysis using Redhawk:

Redhawk performs several types of power analysis on a circuit.
  • Static Voltage (IR) drop with average cycle currents
  • Dynamic Voltage drop with worst-case switching currents
  • Electromigration (EM) Analysis
  • Critical path and clock tree impacts
Redhawk Capabilities:
 As discussed above Redhawk is used to perform EM, IR and transient analysis on power grid. Redhawk is available in different modes. They are
1. Static Mode
2. Dynamic Mode
3. Transient Mode

1. Static Mode: 
 In static mode, Redhawk can perform EM, IR drop analysis. In this mode the tool analyzes average IR Drop and EM in the design.

2. Dynamic Mode:
In Dynamic mode, Redhawk analyzes peak IR drop in the design during functional mode using Vectorless algorithm or VCD. It can also analyze peak IR drop in the design during scanning mode using Vectorless or VCD.

3. Transient Mode:
In Transient mode, Redhawk can perform power up and power down analysis. It analyses peak rush current during turn-on, power grid turn-on time.

Inputs for Redhawk :

  • . LEF
  • . DEF
  • . LIBS
  • . TECH
  • . ploc
  • . GSR
  • . <design>.timing
  • APL files ( cell.spcurrent, cell.cdev)
LEF - Library Exchange Format :
This is a industry standard format that has the information related to pin description and boundaries of the block /instances in the design.

DEF - Design Exchange Format :
This contains logical and physical connectivity between different instances and blocks in the design.

LIB - Synopsys liberty format:
This has several electrical and logical properties for a cell like: input and output pin properties, information on distributing power among the different power pins, internal energy of the cell, cell functionality information, etc.

SPEF - Standard Parasitic Exchange Format:
This file contains the parasitic (RC values) associated with each nets in the design.

It contains Pad location information based on Full-chip Floorplan.

Redhawk Tech file:
It contains Resistance information for all interconnect layers, EM limit information for all interconnect layers, Interconnect Stack information.

APL Files:
It Contains Current Profile characterization data for each standard cell, Intrinsic decap characterization data for each standard cell, Piecewise linear cap characterization data for each standard cell.

It contains STA Timing Information From Primetime. It is Recommended for Static analysis-provides accurate transition times and instance frequency. It required for Dynamic –provides switching windows.

RedHawk outputs:
• IR voltage drop contour maps
• Electro-migration (EM) analysis
• Power density and average current maps
• Text report files of detailed static power, voltage, and current data
• Warnings and violations reports.

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