Saturday, 14 December 2013

IR Drop Analysis Interview Questions

IR Drop Analysis Interview Questions

1. What is IR Drop Analysis? 
A. The power supply in the chip is distributed uniformly through metal layers (Vdd and Vss) across the              design. These metal layers have finite amount of resistance. When voltage is applied to this metal wires          current start flowing through the metal layers and some voltage is  dropped due to that resistance of metal      wires and current. This Drop is called as IR Drop.
     
     For example, a design needs to operate at 2 volts and has a tolerance of 0.4 volts on either side, we need      to ensure that the voltage across its power pin (Vdd) and ground pin (Vss) in that design does not fall            short of 1.6 Volts.The acceptable IR drop in this context is 0.4 volts. That means the design in this                context can allow upto 0.4 volts drop which does not effect the timing and functionality of design. The            process of analyzing this IR Drop is called IR Drop Analysis. 

2. What are the different types of IR Drop Analysis?
A. There are two types of IR Drop Analysis        
           1. Static IR Drop Analysis
           2. Dynamic IR Drop Analysis
      Static IR drop Analysis is vectorless power analysis with average current cycles, whereas, Dynamic IR         drop analysis is vector based power analysis with worst-case switching currents.

3. What are the different tools used for IR Drop Analysis?
A. Various tools are available for IR Drop Analysis. Voltagestorm from Cadence, Redhawk from Apache           are mainly used to show IR Drop on chip.

4. What are the different reasons for high voltage drop in a design?
A. In a design if there is high static or dynamic voltage drop, It could be due to one of the following reasons.

  1. High current flowing through the power grid : can affect Static as well as Dynamic IR drop
  2. High PG grid impedance : can affect static as well as Dynamic IR Drop
  3. Simultaneous Switching : can affect only Dynamic
  4. Insufficient number of voltage sources : can affect Static as well as Dynamic Drop
  5. High Package parasitics : can affect Static as well as Dynamic Drop
  6. Inadequate amount of Decaps available : Can affect only Dynamic
5. How to find the high IR Drop analysis is due to high current flowing through the power (PG) grid?
A. IR Drop is Signal Integrity(SI) effect caused by wire (metal) resistance and current drawn off from Power     (Vdd) and Ground (Vss) grids. Static or Dynamic IR Drop is proportional to the current flowing through       the power grid. High average current can cause for high Static IR Drop. Similarly in dynamic analysis,           high transient(switching) current can lead to high Dynamic IR drop.
  
  Average current is proportional to the average power of the design. High average power can affect both
  static and dynamic voltage drop results. Redhawk power summary report file (adsRpt/power_summary.rpt)   will give you the details of power consumption of the design. Power summary report will give you the             power consumption for each voltage domain, frequency domain and for each cell type in the design.


 Instance power file (adsRpt/<design>.power.rpt) will contain instance specific power values. You
 can also click on any instance in the GUI to get more details of power calculation for that instance.
 In Redhawk GUI, you can see the sorted list of high power instances in the design using “Results
 -> List of Highest Power Instances for Static Simulation” menu.
                                  Figure1. Redhawk Power Summary Report (Source : Apache Redhawk Manual)

You can use the Power Density map (PD) (in figure2) to get the power density distribution in the design. Similarly, Instance power map (IPM) will show you the instance power distribution. Similarly, clock power map (CPM) will show power distribution separately for clock related instances in the design.


                                            Figure2. Redhawk Home page GUI (Source : Apache Redhawk Tool)

Average power has both static and dynamic components. Static component is the leakage power.
  • You can look at the leakage power map (LPM) in the results panel (figure2) to see whether there are any cells with excessive leakage. 
  • From the instance power file (adsRpt/<design>.power.rpt) you can find leakage power component for any instance.
                                 Figure3. Power Density Map (Source : Apache Redhawk Manual)

Dynamic component is contributed by internal power and the switching power. This component is
proportional to the frequency, load and toggle rate. Reason for high dynamic power could be one
of the following:
  • High frequency of switching.
  • High Load capacitance.
  • High toggle rate or BLOCK_POWER_FOR_SCALING used in the analysis.
From the instance power file, you can get the of the power calculation.
  • You can analyze the Instance Frequency Map (IFM) to see whether high frequency is causing high power in some region.
  • Load Cap map (LC) will tell you whether high load is causing the dynamic component of power. High load issue normally happens when you have un-synthesized clock tree or scan chains, with some buffers driving huge fanout load.
  • High toggle rate can also cause high dynamic power. Redhawk derives the toggle rate from one of the following ways.
  • User can scale the power values computed by scaling the TOGGLE_RATE using the
  • GSR keyword BLOCK_POWER_FOR_SCALING. Values specified in this section directly affect your static and dynamic results. 
You can also click on any metal / via segments to see the amount of current flowing through the geometry. Static analysis shows the average current and dynamic analysis shows peak current. In static analysis, it will also show you the current direction. “CUR” Map shows the current distribution throughout the chip.High transient current can be caused by simultaneous switching in the design.

6. How to find the high IR Drop analysis is due to high PG impedance?
A. High Power grid resistance will impede the current flow in the power grid causing high static or dynamic voltage drop. You can use PG Resistance Map (View -> Resistance Maps) to highlight areas with high PG resistance. Also, you can write out the PG Resistance report using the Redhawk command “perform gridcheck”. More details on PG Weakness analysis can be found in the application note “Analyzing PG Weakness Results in Redhawk GUI”.

Redhawk has several features to analyze the structural weakness issues in the power grid. You
can use “View -> Connectivity” menu to analyze PG structural issues such as:
  • Disconnected instances
  • Disconnected wires/vias
  • Shorts
  • Missing vias
                                            Figure4. Connectivity Analysis (Source : Apache Redhawk manual)


When you highlight disconnected instances in Redhawk GUI, instances with VSS disconnect will get highlighted in Blue, VDD disconnect will get highlighted in Green and both VDD/VSS disconnect will get highlighted in Yellow. Corresponding text reports are also available inside adsRpt directory (adsRpt/*.unconnect, adsRpt/apache.missingVias etc).



If there is any major disconnect in the power grid, it will affect the current flow in the design. You can use the current map (CUR button) to review the current flow through the power grid to see whether there are any surprises.



If you are performing RLC extraction on the power grid, high inductance can also cause high dynamic drop. You can perform a dynamic analysis based on RC extraction and compare the results to see whether L component is causing the high drop.

References:
1. Redhawk User's Manual by Apache Design Analysis


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