Thursday, 27 March 2014

High Fanout Net Synthesis (HFNS)

High Fan-out Net Synthesis

Before going to discuss about we have to know the basic terminology like What is Fanout? What are High Fanout Nets (HFN)? Why we are going for High Fanout Net Synthesis (HFNS)?

What is fanout?
Fanout is the number of gate inputs to which the output can be safely connected. i.e., The load that a gate output can drive. The maximum fanout of an output measures it's load-driving capability. Fanout belongs to the output.

What are High Fanout Nets(HFN) ?
High Fanout Nets are the nets which drive more number of load. We set some max fanout limit by using the command set_max_fanout. The nets which have greater than these limit are considered as High Fanout Nets (HFN). Generally clock nets, reset, scan, enable nets are High Fanout Nets.

What is High Fanout Net Synthesis (HFNS)?
High Fanout Net Synthesis (HFNS) is the process of buffering the High Fanout Nets to balance the load.

To balance the load HFNS is perfomed. Too many load affects delay numbers and transition times. Because load is directly proportional to  the delay. By buffering the HFN the load can be balanced. This is called as High Fanout Net Synthesis(HFNS).

Where HFNS ?
Generally at placement step HFNS performed. HFNS can also be performed at synthesis step using Design Compiler. But it's not good idea, Buffers will be removed during PD and again HFNS is performed. It's very time consuming process. So HFNS at synthesis step is not recommended. HFNS at synthesis step gives an idea whether HFN are present in data path or not. Generally HFN are present in clock paths, rest, enable and  scan paths. 

Care that should taken during HFNS:
1. Make sure an appropriate fanout limit is set using set_max_fanout command
2. Verify the SDC used for PD should not have set_ideal_network or set_dont_touch commands on High      Fanout Nets.
3. Use ideal clock network - As clock nets are synthesized separately during Clock Tree Synthesis (CTS)          step, we set clock network as ideal network.


As clock nets are considered as ideal, buffering is not performed on the clock nets even they are High Fanout Nets. So, HFNS is the process of synthesizing other than clock nets, such as reset, scan, test enable nets is called as High Fanout Net Synthesis (HFNS) 


  1. The explanation given in this forum is crisp and clear. Thanks for the post!

  2. Is there any options that we set or procedure that we follow for hfns during placement stage or the tool does by itself. options other than set_max_fanout, set_ideal_nets.