Wednesday, 30 April 2014

Tie Cells Insertion

Tie Cells Insertion

Here I am going to discuss about Tie Cells Insertion. Before going to know about Tie Cells Insertion, We have to know what Tie Cells are. 

Tie Cells:
Tie cells are special purpose standard cells whose output is Constant High or Constant Low. These cells are used to hold (tie) the input of other cells which are required to be connected Constant High (Vdd) or Constant Low (Vss) values.

Tie High Cell:
Tie High Cell is special purpose standard cell whose output is Constant High (Vdd).

Tie Low Cell:
Tie Low Cell is special purpose standard cell whose output is Constant Low (Vss).

There are some unused inputs in the design netlist. These unused inputs should not be floated. They should be tied to either Power (Vdd) or Ground (Vss). The inputs which are required to connect Vdd, connect to Tie High cells. The inputs which are required to connect Vss, connect to Tie Low cells. This is the purpose of Tie cells in the design


Why Tie cells are inserted?
In lower technology nodes the gate oxide of the transistor is so thin and sensitive to voltage fluctuations in the power supply. If the gate of the transistor is directly connected to the Power/Ground network (Power Grid Network), the gate oxide of the transistor might be damaged due to voltage fluctuations in the power supply. To overcome this disadvantage, Tie cells are inserted.

To perform Placement Optimization or Physical optimization, Automatic Insertion and Optimization of Tie offs are required in the design. The following commands are used to execute the same.

set_auto_disable_drc_nets -constant false
set physopt_new_fix_constants true
set_attribute [...] max_fanout 12
set_attribute [...] max_capacitance 0.2 -type float


Tie-off Optimization:
Tie cells optimization means using a tie cell to hold (tie) as many inputs as possible at given logic level, while meeting specified maximum Fanout and maximum capacitance constraints (Logical DRCs). 

The set_auto_disable_drc_nets command enables DRC on constant nets.

The set physopt_new_fix_constants variable to true causes placement tool to observe the maximum capacitance constraint during tie-off optimization.

The maximum capacitance constraint is determined by the max_capacitance attribute, which can be set with the set_max_capacitance or set_attribute command. The set_attribute command can be used to specify explicitly both the maximum fanout and maximum capacitance constraints for objects in the design.


Note: We can also insert tie cells manually with the command connect_tie_cells. The command inserts tie cells and connects them to specified cell ports, while meeting maximum fanout and maximum wire length specified in the command.

Wednesday, 2 April 2014

Congestion in VLSI Physical Design FLow

Congestion in VLSI Physical Design Flow

Here let us discuss about congestion. What is Congestion? What are the reasons for Congestion? How congestion can be fixed?

What is Congestion?
If the number of routing tracks available for routing in one particular area is less than the required routing tracks then the area said to be congested. There will be a limit for number of nets that can be routed through particular area.

What are the reasons for Congestion?
  • High Standard cell density in small area
  • Placement of standard cells near macros
  • High pin density at the edge of macro
  • Bad floorplan
  • During IO optimization tool does buffering, So lot of cells placed in the core area
How congestion can be Analysed?
Congestion can be analysed by using congestion map as shown below figure.

  • If the congestion is not too severe, The actual route can be detoured around congested area. The detoured nets will have worse RC delays than actual VR estimates.
  • If the congestion is too severe, the design can be un-routable. This is really not good. It is important to minimize or eliminate the congestion before continuing.

How to fix Congestion?
  • Rerun the fast placement with Congestion driven option (Congestion driven placement)
  • Modify physical constraints such as adjust cell density in congested areas. Because higher cell density cause for congestion. 
  • Use/Modify proper blockages. i.e., Soft blockages, Hard blockages, Macro Padding are used proper locations to minimize the congestion near macros.
  • Modify floorplaning such as moving macros, change core shape/size, Move pins to give enough room for routing
What happens during congestion driven placement?
As discussed earlier, Congestion driven placement is performed to reduce the congestion. During congestion driven placement, the cells (Higher cell density) which caused for congestion are spread apart. If the cells along timing critical paths are spread apart to minimize congestion, What happens? 

If the cells along timing critical paths spread apart, the timing constraints along that particular paths are not met which cause for timing violations. But these violations can be fixed during incremental optimization. 

What are the care should be taken using congestion driven option?
  • If there is some congestion, use medium effort option
  • If the congestion is bad, use high effort option
  • If there is no congestion, Don't use congestion driven option. If we use congestion driven option in this case, It takes more rum time for placement.
How modify physical constraints reduce congestion?
As discussed earlier, Higher cell density can cause for congestion. By default the cell density can be upto 95%. We can reduce the cell density at congested areas by using coordinate option.
As shown in below figure, we can set cell density to a flexible number to reduce the congestion by using the command 
set_congestion_options - max_util 0.6\
                                        - coordinate {x1 y1 x2 y2}

Here we set the maximum cell density  upto 60% and given the coordinates for the particular area.


How blockages and macro padding(Halos) reduce congestion?
 By using blockages and halos, They prevent the tool placing cells in that particular locations to give enough space for routing near the macros. For more details, please refer Blockages halos post.



Soft Blockages created only for the channels between macros (or) Between macro & the core boundary to give enough space for routing.

Hard blockages always created on the four sides of macro for not to place standard cells or macros near to the macro.
Macro Padding: If the design contains macros that are not placed near another macro (or) the edge of the core then macro padding(Halo) is created. Standard cells cant be placed in this region which give more routing resources to the signal routes.

References:
Synopsys IC Compiler manual