Sunday, 23 February 2014

Different cells used for Low Power Design - Power management Techniques

Level Shifters, Isolation Cells, Retention Registers, Power Switches, Always on Cells 

Level Shifters:

Level Shifters are used in multi voltage design in which more than one voltage supply used. Consider In your design two voltage domains are there. One voltage domain V1 has 1.2V power supply another domain V2 has 1V power supply. Signal has to cross from one domain to another domain while in functional mode. Now assume signal crossing from Low voltage domain V2 to High voltage domain V1, It's logic is interpreted wrongly at V1. To prevent this level shifters are inserted between the different voltage domains for the signals which cross from low voltage domain to High voltage domain and from High voltage domain to low voltage domains.

The main functionality of the level shifters is to shift the voltage one voltage to another voltage level depending upon the the signal crossing different voltage domains.

Isolation Cells:

Isolation cells are used between the domains. Consider there are two domains are in your design i.e,. D1 and D2. The domain D1 is power shut down mode and other domain D2 is in active mode. Since Domain D1 is power down mode it can propagate invalid logic to domain D2. To prevent this, Isolation cells are inserted between the domains to clamp a known value at its output, While domain D1 is shut down mode. Isolation cells should be placed in always on domain to serve it's functionality (clamp the known value to the other domain)

Power Switches:

Power switches are used in power gating technique. As we already discussed in previous post, Power gating is used to reduce the static (Leakage) power in the design. Power gating is performed by shutting down the power for portion of design. Power switches are used to turn off the portions of design which are inactive at a point of time to reduce leakage power.

Retention Registers:

Retention Registers are used to store register states before power down mode. These values will be restored when power is up. So retention cells should be always on to serve the purpose. As these are always on, It can consume power even power down mode. 

Always On cells:

These cells are special cells which should be always on to their purpose.

Thursday, 20 February 2014

Physical Design Flow – Practical Approach with IC Compiler (Synopsys)

Physical Design Flow – Practical Approach with IC Compiler (Synopsys)

The general ICC flow is as shown in figure 1. The first step in ICC Flow is Data Setup. In this step, we create “Container” which is known as “Design Library”.  The inputs which are required for physical design are loaded into this Design Library.  i.e., The Design Library contains Logical/Timing Library files, Physical Library Directories, Constraints, Gate-level Netlist, Technology File, RC (TLU+) Model Files. We provide these Design Library as input to the IC Compiler. The output of the IC Compiler will be Placed, Routed and Optimized layout with Clock Trees as shown in below figure 2.

Inputs for ICC Physical Design Flow:
As shown in figure 2 the inputs for ICC Physical Design flow are logical/Timing libraries, Physical libraries, Technology file, Design Constraints, Gate Level Netlist, RC (TLU+) Model Files. These are given to the ICC tool. Here I am going to discuss about these inputs.

                                                             Figure 2 Inputs and Outputs of ICC Flow

1. Logical/Timing Libraries (.db):
Logical Libraries are library files which provide timing and functionality information of each and every standard cells (AND, OR, Flipflops etc) used in the design. It also provides timing information of hard macros such as IP, ROM, RAM etc. Logical Libraries define and load the Logical DRC such as Maximum fanout, Maximum Transistion, Min/Max Capacitances. Logical libraries are also used at Synthesis step in DC. These are in .db form. Logical libraries are specified by the variables target_library and link_library.

2. Physical/Reference Libraries (Milkyway .db):
Physical/Reference libraries contain Physical Information of standard, macro and pad cells, which is necessary for placement and routing. These libraries define placement tile (Height of placement rows, minimum width resolution, preferred routing direction, Pitch of routing tracks etc). These libraries are specified with command create_mw_lib –mw_reference_library. 

3. Technology file:
A Technology file is provided by the technology vendor. Technology file is unique for each technology. Technology file contains the information related to metal/via information such as
·         Units and precision for electrical units (Voltage,  Current, Power etc)
·         Define colors and patterns of layers for display
·         Number and Name designations for each metal/via
·         Physical and Electrical characteristics of each metal/via
·         Define Design rules such as minimum wire  widths and minimum wire to wire spacing 
·         Contains ERC rules, Extraction Rules, LVS rules
·         Provide parameterized cells (PCELLs) for MOS, caps etc
·         Create menus and commands (Ex: create contact)
4. RC (TLU+) Model:

ICC calculates delay for every net and every cell. To calculate delay tool needs each net R’s and Capacitances. IC Compiler calculates interconnect R and C values using net geometry and TLU+ look up tables. It models UDSM process effects. TLU+ is a binary table which has R and C values for delay calculation.

5. Netlist:
It can be in the form of Verilog or VHDL(.v or,vhdl). This netlist is produced during logical synthesis, which takes place prior to the physical design stage.
6. Constraints:
Design constraints (like system clock definition and clock delays, Multiple cycle paths, Input and output delays, Minimum and maximum path delays, Input transition and output load capacitance, False paths) are identical to those which were used during the front-end logic synthesis stage prior to physical design. It is available in the form of SDC (Synopsys Design Constraints).