Wednesday, 30 April 2014

Tie Cells Insertion

Tie Cells Insertion

Here I am going to discuss about Tie Cells Insertion. Before going to know about Tie Cells Insertion, We have to know what Tie Cells are. 

Tie Cells:
Tie cells are special purpose standard cells whose output is Constant High or Constant Low. These cells are used to hold (tie) the input of other cells which are required to be connected Constant High (Vdd) or Constant Low (Vss) values.

Tie High Cell:
Tie High Cell is special purpose standard cell whose output is Constant High (Vdd).

Tie Low Cell:
Tie Low Cell is special purpose standard cell whose output is Constant Low (Vss).

There are some unused inputs in the design netlist. These unused inputs should not be floated. They should be tied to either Power (Vdd) or Ground (Vss). The inputs which are required to connect Vdd, connect to Tie High cells. The inputs which are required to connect Vss, connect to Tie Low cells. This is the purpose of Tie cells in the design


Why Tie cells are inserted?
In lower technology nodes the gate oxide of the transistor is so thin and sensitive to voltage fluctuations in the power supply. If the gate of the transistor is directly connected to the Power/Ground network (Power Grid Network), the gate oxide of the transistor might be damaged due to voltage fluctuations in the power supply. To overcome this disadvantage, Tie cells are inserted.

To perform Placement Optimization or Physical optimization, Automatic Insertion and Optimization of Tie offs are required in the design. The following commands are used to execute the same.

set_auto_disable_drc_nets -constant false
set physopt_new_fix_constants true
set_attribute [...] max_fanout 12
set_attribute [...] max_capacitance 0.2 -type float


Tie-off Optimization:
Tie cells optimization means using a tie cell to hold (tie) as many inputs as possible at given logic level, while meeting specified maximum Fanout and maximum capacitance constraints (Logical DRCs). 

The set_auto_disable_drc_nets command enables DRC on constant nets.

The set physopt_new_fix_constants variable to true causes placement tool to observe the maximum capacitance constraint during tie-off optimization.

The maximum capacitance constraint is determined by the max_capacitance attribute, which can be set with the set_max_capacitance or set_attribute command. The set_attribute command can be used to specify explicitly both the maximum fanout and maximum capacitance constraints for objects in the design.


Note: We can also insert tie cells manually with the command connect_tie_cells. The command inserts tie cells and connects them to specified cell ports, while meeting maximum fanout and maximum wire length specified in the command.

Wednesday, 2 April 2014

Congestion in VLSI Physical Design FLow

Congestion in VLSI Physical Design Flow

Here let us discuss about congestion. What is Congestion? What are the reasons for Congestion? How congestion can be fixed?

What is Congestion?
If the number of routing tracks available for routing in one particular area is less than the required routing tracks then the area said to be congested. There will be a limit for number of nets that can be routed through particular area.

What are the reasons for Congestion?
  • High Standard cell density in small area
  • Placement of standard cells near macros
  • High pin density at the edge of macro
  • Bad floorplan
  • During IO optimization tool does buffering, So lot of cells placed in the core area
How congestion can be Analysed?
Congestion can be analysed by using congestion map as shown below figure.

  • If the congestion is not too severe, The actual route can be detoured around congested area. The detoured nets will have worse RC delays than actual VR estimates.
  • If the congestion is too severe, the design can be un-routable. This is really not good. It is important to minimize or eliminate the congestion before continuing.

How to fix Congestion?
  • Rerun the fast placement with Congestion driven option (Congestion driven placement)
  • Modify physical constraints such as adjust cell density in congested areas. Because higher cell density cause for congestion. 
  • Use/Modify proper blockages. i.e., Soft blockages, Hard blockages, Macro Padding are used proper locations to minimize the congestion near macros.
  • Modify floorplaning such as moving macros, change core shape/size, Move pins to give enough room for routing
What happens during congestion driven placement?
As discussed earlier, Congestion driven placement is performed to reduce the congestion. During congestion driven placement, the cells (Higher cell density) which caused for congestion are spread apart. If the cells along timing critical paths are spread apart to minimize congestion, What happens? 

If the cells along timing critical paths spread apart, the timing constraints along that particular paths are not met which cause for timing violations. But these violations can be fixed during incremental optimization. 

What are the care should be taken using congestion driven option?
  • If there is some congestion, use medium effort option
  • If the congestion is bad, use high effort option
  • If there is no congestion, Don't use congestion driven option. If we use congestion driven option in this case, It takes more rum time for placement.
How modify physical constraints reduce congestion?
As discussed earlier, Higher cell density can cause for congestion. By default the cell density can be upto 95%. We can reduce the cell density at congested areas by using coordinate option.
As shown in below figure, we can set cell density to a flexible number to reduce the congestion by using the command 
set_congestion_options - max_util 0.6\
                                        - coordinate {x1 y1 x2 y2}

Here we set the maximum cell density  upto 60% and given the coordinates for the particular area.


How blockages and macro padding(Halos) reduce congestion?
 By using blockages and halos, They prevent the tool placing cells in that particular locations to give enough space for routing near the macros. For more details, please refer Blockages halos post.



Soft Blockages created only for the channels between macros (or) Between macro & the core boundary to give enough space for routing.

Hard blockages always created on the four sides of macro for not to place standard cells or macros near to the macro.
Macro Padding: If the design contains macros that are not placed near another macro (or) the edge of the core then macro padding(Halo) is created. Standard cells cant be placed in this region which give more routing resources to the signal routes.

References:
Synopsys IC Compiler manual

Thursday, 27 March 2014

High Fanout Net Synthesis (HFNS)

High Fan-out Net Synthesis

Before going to discuss about we have to know the basic terminology like What is Fanout? What are High Fanout Nets (HFN)? Why we are going for High Fanout Net Synthesis (HFNS)?

What is fanout?
Fanout is the number of gate inputs to which the output can be safely connected. i.e., The load that a gate output can drive. The maximum fanout of an output measures it's load-driving capability. Fanout belongs to the output.

What are High Fanout Nets(HFN) ?
High Fanout Nets are the nets which drive more number of load. We set some max fanout limit by using the command set_max_fanout. The nets which have greater than these limit are considered as High Fanout Nets (HFN). Generally clock nets, reset, scan, enable nets are High Fanout Nets.

What is High Fanout Net Synthesis (HFNS)?
High Fanout Net Synthesis (HFNS) is the process of buffering the High Fanout Nets to balance the load.

Why HFNS?
To balance the load HFNS is perfomed. Too many load affects delay numbers and transition times. Because load is directly proportional to  the delay. By buffering the HFN the load can be balanced. This is called as High Fanout Net Synthesis(HFNS).

Where HFNS ?
Generally at placement step HFNS performed. HFNS can also be performed at synthesis step using Design Compiler. But it's not good idea, Buffers will be removed during PD and again HFNS is performed. It's very time consuming process. So HFNS at synthesis step is not recommended. HFNS at synthesis step gives an idea whether HFN are present in data path or not. Generally HFN are present in clock paths, rest, enable and  scan paths. 

Care that should taken during HFNS:
1. Make sure an appropriate fanout limit is set using set_max_fanout command
2. Verify the SDC used for PD should not have set_ideal_network or set_dont_touch commands on High      Fanout Nets.
3. Use ideal clock network - As clock nets are synthesized separately during Clock Tree Synthesis (CTS)          step, we set clock network as ideal network.

NOTE:

As clock nets are considered as ideal, buffering is not performed on the clock nets even they are High Fanout Nets. So, HFNS is the process of synthesizing other than clock nets, such as reset, scan, test enable nets is called as High Fanout Net Synthesis (HFNS) 

Sunday, 23 February 2014

Different cells used for Low Power Design - Power management Techniques

Level Shifters, Isolation Cells, Retention Registers, Power Switches, Always on Cells 


Level Shifters:

Level Shifters are used in multi voltage design in which more than one voltage supply used. Consider In your design two voltage domains are there. One voltage domain V1 has 1.2V power supply another domain V2 has 1V power supply. Signal has to cross from one domain to another domain while in functional mode. Now assume signal crossing from Low voltage domain V2 to High voltage domain V1, It's logic is interpreted wrongly at V1. To prevent this level shifters are inserted between the different voltage domains for the signals which cross from low voltage domain to High voltage domain and from High voltage domain to low voltage domains.

The main functionality of the level shifters is to shift the voltage one voltage to another voltage level depending upon the the signal crossing different voltage domains.


Isolation Cells:

Isolation cells are used between the domains. Consider there are two domains are in your design i.e,. D1 and D2. The domain D1 is power shut down mode and other domain D2 is in active mode. Since Domain D1 is power down mode it can propagate invalid logic to domain D2. To prevent this, Isolation cells are inserted between the domains to clamp a known value at its output, While domain D1 is shut down mode. Isolation cells should be placed in always on domain to serve it's functionality (clamp the known value to the other domain)


Power Switches:

Power switches are used in power gating technique. As we already discussed in previous post, Power gating is used to reduce the static (Leakage) power in the design. Power gating is performed by shutting down the power for portion of design. Power switches are used to turn off the portions of design which are inactive at a point of time to reduce leakage power.


Retention Registers:

Retention Registers are used to store register states before power down mode. These values will be restored when power is up. So retention cells should be always on to serve the purpose. As these are always on, It can consume power even power down mode. 


Always On cells:

These cells are special cells which should be always on to their purpose.

Thursday, 20 February 2014

Physical Design Flow – Practical Approach with IC Compiler (Synopsys)

Physical Design Flow – Practical Approach with IC Compiler (Synopsys)


The general ICC flow is as shown in figure 1. The first step in ICC Flow is Data Setup. In this step, we create “Container” which is known as “Design Library”.  The inputs which are required for physical design are loaded into this Design Library.  i.e., The Design Library contains Logical/Timing Library files, Physical Library Directories, Constraints, Gate-level Netlist, Technology File, RC (TLU+) Model Files. We provide these Design Library as input to the IC Compiler. The output of the IC Compiler will be Placed, Routed and Optimized layout with Clock Trees as shown in below figure 2.

Inputs for ICC Physical Design Flow:
As shown in figure 2 the inputs for ICC Physical Design flow are logical/Timing libraries, Physical libraries, Technology file, Design Constraints, Gate Level Netlist, RC (TLU+) Model Files. These are given to the ICC tool. Here I am going to discuss about these inputs.

                                                             Figure 2 Inputs and Outputs of ICC Flow

1. Logical/Timing Libraries (.db):
Logical Libraries are library files which provide timing and functionality information of each and every standard cells (AND, OR, Flipflops etc) used in the design. It also provides timing information of hard macros such as IP, ROM, RAM etc. Logical Libraries define and load the Logical DRC such as Maximum fanout, Maximum Transistion, Min/Max Capacitances. Logical libraries are also used at Synthesis step in DC. These are in .db form. Logical libraries are specified by the variables target_library and link_library.

2. Physical/Reference Libraries (Milkyway .db):
Physical/Reference libraries contain Physical Information of standard, macro and pad cells, which is necessary for placement and routing. These libraries define placement tile (Height of placement rows, minimum width resolution, preferred routing direction, Pitch of routing tracks etc). These libraries are specified with command create_mw_lib –mw_reference_library. 


3. Technology file:
A Technology file is provided by the technology vendor. Technology file is unique for each technology. Technology file contains the information related to metal/via information such as
·         Units and precision for electrical units (Voltage,  Current, Power etc)
·         Define colors and patterns of layers for display
·         Number and Name designations for each metal/via
·         Physical and Electrical characteristics of each metal/via
·         Define Design rules such as minimum wire  widths and minimum wire to wire spacing 
·         Contains ERC rules, Extraction Rules, LVS rules
·         Provide parameterized cells (PCELLs) for MOS, caps etc
·         Create menus and commands (Ex: create contact)
4. RC (TLU+) Model:

ICC calculates delay for every net and every cell. To calculate delay tool needs each net R’s and Capacitances. IC Compiler calculates interconnect R and C values using net geometry and TLU+ look up tables. It models UDSM process effects. TLU+ is a binary table which has R and C values for delay calculation.

5. Netlist:
It can be in the form of Verilog or VHDL(.v or,vhdl). This netlist is produced during logical synthesis, which takes place prior to the physical design stage.
6. Constraints:
Design constraints (like system clock definition and clock delays, Multiple cycle paths, Input and output delays, Minimum and maximum path delays, Input transition and output load capacitance, False paths) are identical to those which were used during the front-end logic synthesis stage prior to physical design. It is available in the form of SDC (Synopsys Design Constraints).