Tuesday, 27 August 2020

IR Drop Analysis

What is IR Drop Analysis? How it effects the timing?

The power supply in the chip is distributed uniformly through metal layers (Vdd and Vss) across the design. These metal layers have finite amount of resistance. When voltage is applied to this metal wires current start flowing through the metal layers and some voltage is  dropped due to that resistance of metal wires and current. This Drop is called as IR Drop. For example, a design needs to operate at 2 volts and has a tolerance of 0.4 volts on either side, we need to ensure that the voltage across its power pin (Vdd) and ground pin (Vss) in that design does not fall short of 1.6 Volts.The acceptable IR drop in this context is 0.4 volts. That means the design in this context can allow upto 0.4 volts drop which does not effect the timing and functionality of design.

How it effects the timing?
IR Drop is Signal Integrity(SI) effect caused by wire resistance and current drawn off from Power (Vdd) and Ground (Vss) grids. According to Ohms law, V = IR. If wire resistance is too high or the current passing through the metal layers is larger than the predicted, an unacceptable Voltage drop may occur. Due to this un acceptable voltage drop, The power supply voltage decreases. That means the required power across the design is not reaching to the cells. This results in increased noise susceptibility and poor performance.

The design may have different types of gates with different voltage levels. As the voltage at gates decreased due to unacceptable voltage drop in the supply voltage, the gate delays are increased non-linearly. This may lead to setup time and hold time violations depending on which path these gates are residing in the design. As technology node shrinking, there is decrease in the geometries of the metal layers and the resistance of this wires increased which lead to decrease in power supply voltage. During Clock Tree Synthesis, the buffers and inverters are added along the clock path to balance the skew. The voltage drop on the buffers and inverters of clock path will cause the delay in arrival of clock signal, resulting hold violation.

What are the tools used for IR Drop Analysis? In which stage IR Drop Analysis performed ?

Various tools are available for IR Drop Analysis. Voltagestorm from Cadence, Redhawk from Apache are mainly used to show IR Drop on chip. Here we are going to discuss about IR Drop using Redhawk. IR Drop Analysis using Redhawk is possible at different stages of the design flow. When changes are in expensive and they don't effect project's schedule, It is better to use Redhawk for IR drop analysis from start of the design cycle. It can identify and fix power grid problems in the design. This also reduces changes required in sign-off stage where final static and dynamic voltage (IR) drops performed. So Redhawk can be used anywhere in the design starting from the floorplanning stage through initial and final cell placement stages.

Wednesday, 21 August 2020

Basic Terminology in Physical Design

Design: A circuit that performs one or more logical functions.

Cell: An instance of a design or library primitive within a design.

Port: The input or output of a design.

Pin: The input or output of a cell.

Net: A wire that connects ports to ports or ports to pins.

Clock: A timing reference object to describe a waveform for timing analysis.

Logical Libraries: Logical libraries are libraries which provide

  • Timing and functionality information for all standard cells (like AND, OR, Flipflops)
  • Timing information for Hard Macros (IP, ROM, RAM)
  • Define drive/load design rules ( Max Transition, Max Fanout, Max/Min Capacitance)   
Physical Libraries: Physical libraries are libraries which contain
  • Physical Information of Standard cells and Macro cells necessary for placement
  • Define placement unit tile 
Standard Cell: A standard cell is a group of transistors and interconnect structures that provides a boolean logic function (e.g., ANDORXORXNOR, inverters) or a storage function (flipflop or latch). 

Macro: Macros are intellectual properties that can be directly used in the design. These are need not to be design. For example memories, processor core, PLL etc. A macro can be hard or Soft macro.

Target Library: A technology library that Design Compiler maps to during optimization. Along with the link_library and search_path variables, you need to specify the logical library that will be used for mapping/optimization.

Link Library : The technology library that contains the definition of the cells used in the mapped
design. In principle should be the same as target_library unless a technology translation is being performed.

Search Path: If the library variables only specify file names, search_path is used to locate libraries. By default points to current working directory. By default, you must specify the unix-path for all files (relative or absolute). It specifies where to look for files.

Constraints: Constraints are the instructions that the designer can apply during various steps in the VLSI chip implementation, such as logic synthesis, Clock Tree synthesis (CTS), Place & Route, and Static Timing Analysis (STA).
Constraints are 2 types
  1. Design Rule Constraints
  2. Optimization Constraints  
Design Rule Constraints:
  • These are implicit constraints.
  •  The technology library (.lib) defines them. 
  • These constraints are requirements for a design to them. 
  • These constraints are requirements for a design to function correctly, and they apply to any design using the library. 
  • You can make these constraints more restrictive than optimization constraints.
Different types of Design Rule Constraints are
  1. Maximum Transition time
  2. Maximum Fanout
  3. Maximum/Minimum Capacitance
  4. Cell Degradation
Optimization Constraints:
  • These are explicit constraints; 
  • Designer define them. 
  • Optimization constraints apply to the design on which you are working for the duration of the dc_shell session and represent the design’s goals. 
  • They must be realistic.
  • Optimization Constraints describe the design goals (Area, Timing etc)
Maximum Transition time:
The maximum transition time for a net is the longest time required for its driving pin to change logic values. Typically fixed by buffering the output of driving gate. 

Maximum Fanout:
The maximum fanout of an output measures it's load driving capability. Most technology libraries (.lib) place fanout restrictions on driving pins, creating an implicit fanout constraint for every driving pin in designs using that library. Design Compiler models fanout restrictions by associating a fanout_load attribute with each input pin and a max_fanout attribute with each output (driving) pin on a cell.

Maximum Capacitance:
The maximum total capacitance that an output pin can drive. The maximum capacitance design rule constraint allows you to control the capacitance of nets  directly. (The design rule constraints max_fanout and max_transition limit the actual capacitance of nets indirectly.)

Minimum Capacitance:
The min_capacitance design rule specifies the minimum load a cell can drive. It specifies the lower bound of the range of loads with which a cell has been characterized to operate.

Optimization Constraints:

Timing Constraints:
Timing Constraints are required to communicate the design’s timing intentions to IC Compiler. They should be the same ones used for synthesis with Design Compiler (preferably SDC).

Synopsys Design Constraints (SDC):
A format used to specify the design intent including the timing, power and area constraints of a design. SDC is tool based. SDC contains 4 types of information.
  1. SDC Version
  2. SDC units
  3. Design Constraints
SDC version:
It sets the the version. Default version is 1.9

SDC units:
It specifies the units for capacitance, resistance, time, voltage, current and power.

Design Constraints:
The following are the design constraints are specified in SDC
                 1. system clock definition
                 2. clock delays
                 3. Multi Cycle Paths
                 4. Input & output delays
                 5. Minimum & Maximum path delays
                 6. Input transition and output load capacitance
                 7. False paths

Clock Tree Synthesis (CTS):
CTS is the process of inserting buffers/inverters along the clock paths of the design in order to balance the skew and to minimize insertion delay.
Skew: Skew is the difference in arrival of clock at two consecutive pins of a sequential element.

Positive skew- If capture clock comes late than launch clock then it is called positive skew.

Negative skew-If capture clock comes early than launch clock it is called -ve skew.
Local skew- It is the difference in arrival of clock at two consecutive pins of a sequential element.
Global skew- It is Defined as the difference between max insertion delay and the min insertion delay of any flops.
Boundary skew-It is defined as the difference between max insertion delay and the min insertion delay of boundary flops.
Useful skew-If clock is skewed intentionally to resolve violations, it is called useful skew.
Latency- Latency is the delay of the clock source and clock network delay.
Source latency- The delay from the clock origin point to the clock definition point in the design.
Network latency- The delay from the clock definition point to the clock pin of the register.
Uncertainity- Clock uncertainty is the time difference between the arrivals of clock signals at registers in one clock domain or between domains.
Jitter- Jitter is the short-term variations of a signal with respect to its ideal position in time. It is the variation of the clock period from edge to edge.

Setting Operating conditions:

1. Process Variation:
Variations in the process parameters, such as impurity concentration densities, oxide thicknesses, and diffusion depths. These are caused by non-uniform conditions during the deposition and/or the diffusion of the impurities. This introduces variations in the sheet resistances and transistor parameters such as the threshold voltage Variations in the dimensions of the devices, mainly resulting from the limited resolution of the photo lithographic process. This causes (W/L) variations in MOS transistors and mismatches in the emitter areas of bipolar devices.
2. Supply Voltage Variation
3. Ambient temperature Variations
4. It is important to analyze the design for best case and worst case scenarios. Best case to find issues with hold time violations and worst case to find issues with setup violations.

Timing Analysis:
Timing analysis is a method of validating the timing performance of a design  by checking the timing paths for timing violations. 

Net Delay: Interconnect relationships between a driver pin and its fanout
In the absence of physical design information, the timing analyser in Synopsys uses statistically generated wire load models to estimate wire lengths in a design. Two important concepts behind wire load models are
1. Wire load models provide a fanout to length relationship. So by knowing fanout, one can estimate the            length.
2. capacitance and resistance per unit length are given and the estimated length is then translated into                 estimated R and C values to give an estimated delays.
Wire load models are area dependent. Larger the area, greater the R and C value per unit length.

Cell Delay: 
  • Timing relationships between an input pin and an output pin, or between an output pin and another output pin of the same gate. 
  • Cell delay is calculated using non-linear delay models, which are stored in the ‘LM’ view of each cell. 
  • NLDM is highly accurate as it is derived from SPICE characterizations. 
  • The delay is a function of the input transition time of the cell (TInput) [also called slew], the driving strength of the cell (RCell), the wire capacitance (CNet) and the pin capacitance of the receivers (CPin). 
  • A slow input transition time will slow the rate at which the cell’s transistors can change state (from “on” to “off”), as well as a large output load (Cnet + Cpin), thereby increasing the “delay” of the logic gate. 

There is another NLDM table in the library to calculate output transition. Output transition of a cell becomes the input transition of the next cell down the chain.

CMOS Delay Model:  
   Transition Time = Drive R * Load C
   Cell Delay = f(Input Transition Time, Cnet + Cpin)
   Net Delay = f(Rnet, Cnet + Cpin)

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Friday, 2 August 2020

Low Power Design

Power Planning:

Power is limiting factor affection performance and features in most important products. When you decided to buy a mobile, What are the features you look for? The mobile should have camera (primary or secondary), 3G/4G support, and all the features. Apart from these features, The mobile should be light weight(portable), long battery life. For suppose you have to travel long distance, you are carrying your mobile. If the battery of mobile lasts in few hours. Then you hate to charge the battery again and again. To make battery lasts for long time, Low power design comes into the picture. Power management issues are affecting every aspect of of the design. They can be
  • Architecture
  • Design Techniques
  • Process Technology
  • Design methodology
  • Software
Challenges of Low Power:
  • Lowering Supply Voltage
  • Increasing Device Densities as Technology Node Shrinking
  • Increasing Clock Frequencies
  • Lowering Transistor Threshold Voltage

Components of Power:
  • Static Power
  • Dynamic Power
  • Total Power Consumption
Total Power consumption = Static power consumption + Dynamic Power Consumption

1. Dynamic Power:

  • During the switching of Transistors
  • Depends upon the clock frequency and switching activity 
  • Consisting of switching and internal power
  • Dynamic power consumption is given by
So Dynamic power depends on the Load capacitance, Clock frequency and operating voltage.

Dynamic power can be reduced by lowering operating voltage (Vdd), lowering switching activity and lowering switch capacitance (C load).

Load capacitance (C load) depends on 
  1. Output node capacitance of the logic gate (Due to the drain diffusion region)
  2. Total interconnects and capacitance ( Has higher effects as technology node shrinks)
  3. Input node capacitance of the driven gate ( Due to gate oxide capacitance)
Internal Power:
 Power consumed by the cell when input changes, but the output doesn't change. Lower threshold voltages and slower transitions result in more internal power consumption.

Short Circuit Power:
For finite rise and fall time, When Vtn < Vin < (Vdd-Vtp) holds, there will be a conductive path open between Vdd and GND because both the nMOS and pMOS devices will be simultaneously on. 

Short-circuit power is typically estimated as:

This short circuit power component is usually not significant in logic design, but it appears in transistors that are used to drive large capacitances, such as bus wires and especially off-chip circuitry. As wires on chip became narrower, long wires became more resistive. CMOS gates at the end of those resistive wires see slow input transitions.

To minimize the total average short circuit current, it is desirable to have equal input and output edge times. In this case, the power consumed by the short circuit current is typically less than 10% of the total dynamic power. An important point to note is that if the supply is lowered to below the sum of the thresholds of the transistors, Vdd<Vthn+|Vthp|, the short circuit currents can be eliminated because both devices will never be on at the same time for any input voltage value.By balancing transistor size we can get equal Rise time and fall time. 

2. Static Power:
  • Transistor leakage current that flows whenever power is applied to the device
  • Independent of the clock frequency and switching activity
  • Static power is given by

Static Power can be reduced by lowering operating voltage and using fewer leaking transistors.

Leakage Power :

The power consumed by the sub threshold currents and by reverse biased diodes in a CMOS transistor is considered as leakage power. The leakage power of a CMOS logic gate does not depend on input transition or load capacitance and hence it remains constant for a logic cell.

There are different low power design techniques to reduce the above power components
Dynamic power component can be reduced by the following techniques                     
               1. Clock gating
               2. Voltage and Frequency Scaling (DVFS, SVFS)
               3. Gate Sizing
               4. Multi Vdd
Static (Leakage) power component can be reduced by the following techniques 

               1. Multi Vt
               2. Power Gating
               3. Use new devices like Finfet and SOI
               4. Back (Substrate) Bias

We will discuss about these techniques in our next blogs in detail. Now Android Application available, Click here to download it

Thursday, 1 August 2020

Blockages and Halos


Blockages are specific locations where placing of cells are prevented or blocked. These act as guidelines for placing std cells in the design. Blockages will not be guiding the placement tool to place std cell at some particular area, but it wont allow placement tool to place std cells at specified locations. This way blockages are act as guidelines to the placement tool.

Blockages are of following types

  • Soft ( Non-Buffer ) Blockage
  • Hard ( std cell) Blockage
  • Partial Blockage
  • Placement Blockage
  • Routing Blockage
Soft Blockage :

Soft Blockage specifies a region where only buffers can be placed. That means standard cells cannot be placed in this region. It blocks (prevents) the placement tool from placing non-buffer cells such as standard cells in this region.

Hard Blockage :

Hard blockage specifies a region where all standard (std) cells and buffers cannot be placed. It prevents the placement tool from placing std cells and buffers in this region.

 Hard blockages are mostly used to

  • Block std cells to certain regions in the design
  • Avoid routing congestion at macro corners
  • Control power rail generations at macro corners
Partial Blockages: 

The blockage factor for any blockage is 100% by default. So no cells can be placed in that region, but the flexibility of blockages can be chosen by Partial Blockages. To reduce placement density without blocking 100% of area, changing the blockage factor of an existing region to flexible value will be a better option.

Placement Blockage:

Placement blockage prevent the placement tool from placing cells at specific regions. Placement blockages are created at floor planning stage. 

Placement blockages are used to
  • Define standard cells and Macro Area
  • Reserve channels for buffer insertion
  • Prevent cells from being placed nearer to macros
  • Prevent congestion near macros
Routing Blockage:

Routing blockages block routing resources on one or more layers. It can be created at any point in the design.

HALO ( Keep-Out Region): 

  1. HALO is the region around the boundary of fixed macro in the design in which no other macro or std cells can be placed. Halo allows placement of buffers and inverters in its area. 
  2. Halos of two adjacent macros can be overlap. 
  3. If the macros are moved from one place to another place, Halos will also be moved. But in the case of blockages if the macros are moved from one place to another place the blockages cannot be moved. 
Now Android Application available, Click here to download it