Monday, 7 October 2013

Power Gating - Power Management Technique

Power Gating:

Power Gating is a low power technique in deep sub micron technologies. Power Gating is performed by shutting down the power for a portion of the design in order to reduce the static(leakage) power in the design. Power Switch (PS) cell is  basic element which is used in power gating technique to shutting down the power for a portion of the design. The PS cell is also known as power management cell. The basic idea of power gating is to separate the VDD or GND power supply from standard cells of a specific design hierarchy.

Appropriate sized PMOS(Header) or NMOS(Footer) transistors are used as Power Switch (PS) cells. These two NMOS, PMOS cells only differ in the fact that the switches switch different power rails VDD and VSS respectively as shown in below Figure1. The designer turned to use header switches since header switches have less leakage and they are also more easy for implementation.


                                                        Figure 1. Power Gating

Switch cell has two modes of operation  - ON or OFF
When switches are in off state, they disconnect the devices inside the block from power source. This reduces the leakage current flow in the devices of the block.

There are two approaches in Power Gating.
    1. Fine Grain Power Gating
    2. Coarse Grain Power Gating

In Fine Grain Power Gating Technique, Each standard cell has inbuilt power switch. Where in Coarse Grain technique switches control entire block of standard cells using a large size transistor. Each of these approaches has their various trade-offs. Fine grain is easier to implement in terms of timing analysis, but with significant area overhead resulting in higher fabrication cost.On the other hand, the coarse grain switches require more consideration in terms of timing and wake-up time, but shows grater leakage saving. The coarse grain power gating is common implementation technique nowadays and can reduce leakage current by 30X.

Power Switches Placement Styles:

Coarse grain implementation provides multiple placement topologies for the power switches. For example, switches can be placed around the power domain (in a column or ring way) or in an array fashion inside the domain area. Array style is a more common technique as it yields smaller IR-drop and less area. It is also more efficient with respect to Power-Gates control sequence. On the other hand, ring approach can eliminate the user from synthesizing complicated Power-Grid and it also gives better placement results, as it removes fragmentations from placement areas.

Array style also suits best Flip-Chip designs, where Power is delivered from the Bond pads placed also inside the core, which reduce IR-drop significantly, when compared to ring placement style.

Low power Cells:

To facilitate data transfer between multiple Power domains operating at different voltage levels, it is recommended to use level-shifters. Usually both low-to-high and high-to-low level shifters are provided by library vendors.
Level shifters are used for two main reasons. First of all, when a signal propagates from a low-voltage block to a high-voltage block, a lower voltage at the PMOS gate might result in the gate not being entirely switched off, which can cause abnormal leakage current. Secondly, because signals must transition across voltage domains, levels shifters should be used to ensure that both net transition and net delays are accurately calculated.

For power domains which share the same operating voltage but some of them may be shut-off, an isolation cell is required on power domain interface. The reason for this is that cells connected to power-off blocks, their inputs become floating which may cause high leakage power. Therefore, isolation cells are necessary to isolate floating inputs. The isolation is performed by setting a default logic value on the output depends on the state of a dedicated control pin. Usually 2 types of isolation cells are provided by the library vendor: clamp0 and clamp1, which differs by the default value, set in isolation state. Desired cell type is chosen according to the functionality on the receiver side.

Blocks operate at different voltage levels, and some of them can also be turned off, requires both isolation and level-shifting functions at the power domain interface. To simplify implementation, library vendors usually supply a single cell called the enable-level shifter, which is basically a level-shifter that includes an enable signal.

The recommendation is to place Enable Level Shifters on all outputs of such blocks. Both Isolation cells and Enable Level Shifters are placed on the Always-on area. Figure 2 illustrates Low-Power cells usage between various types of power domains.
                                                   Figure 2. Low power cells usage

Power Switch Count:

In order to ensure correct operation under functional mode, we need to make sure no I/R drop is within cell characterization range (usually 10% of Nominal voltage). Since Power switches are in linear state when they are turned ON, they act like a resistor which drops the Voltage based on its resistance, as described in figure 3.

                                            Figure 3. IR Drop through Power Switch
Minimal number of power switches can be determined from the following data:
  • DC I/V curve (Transistors are in linear state)
  • IR drop limit for the switches
  • Domain power consumption

One can use the following formula to derive the minimum number of switches required for a
design when the above data is given as input.


Additional optimization can be made for leakage/Performance trade-off. While large number of
switches increases total leakage & area, insufficient number of switches increase IR drop and
degrades performance.

References:

1. Robust Power Gating Implementation using ICC by Ariel Wolf, SNUG Israel 2009.

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