Tuesday, 8 October 2013

Placement

Placement
Placement is the process of placing standard cells in the rows created at floorplanning stage. The goal is to minimize the total area and interconnect cost. The quality of routing is highly determined by the placement. Placement becomes very critical in Deep Sub Micron technologies.The inputs for the placement stage are Gate-level Netlist, Floorplanned design, Design libraries (Physical and Logical libraries), Design Constraints, Technology file.


Gate-Level Netlist:

Gate-level netlist contain references to standard cells and macros, which are stored in the logical libraries, as well as other hierarchical logic blocks. Before placing one must ensure that all references can be resolved.

Reference Libraries:
Reference Libraries contain logical and physical information of macros, standard cells used by many other designs. These are referenced by pointers in the design library for memory efficiency. A standard cell library also contains a corresponding abstract view for each layout view.

Placement is the process of finding a suitable physical location for each cell in the design. Placement is performed in two stages: coarse placement and legalization.

Coarse Placement:
During coarse placement, The placement tool determines an approximate location for each cell according to the timing and congestion constraints. The placed cells do not fall on the placement grid and may overlap each other. Large cells, such as RAM and IP blocks, act as placement blockages for smaller, leaf-level cells. Coarse placement is fast and is sufficiently accurate for initial timing and congestion analysis

Legalization:
During legalization, Placement moves the cells to precisely legal locations on the placement grid and eliminates any overlap between cells. The small changes to cell locations cause the lengths of the wire connections to change, possibly causing new timing violations. Such violations can often be fixed by incremental optimization, for example, by re-sizing the driving cells. 

The place_opt command is recommended for performing placement in most situations. This command performs coarse placement, high-fanout net synthesis, physical optimization, and legalization, all in a single operation. In certain applications, you might want to perform placement tasks individually using commands such as create_placementand physopt, for a greater degree of control or to closely monitor the results as they are generated.

In the placement process, placement tool considers possible trade-offs between timing and congestion. Timing considerations bring cells closer together to minimize wire lengths and therefore wire delays. On the other hand, the occurrence of congestion draws cells further apart to provide room for the connections. Congestion cannot be ignored entirely in favor of timing because rerouting wires around congested areas will cause an increase in wire lengths and wire delays, thus defeating the value of close placement.


In the place_opt command, the -congestion option causes the tool to apply more effort to congestion removal, resulting in better routability. However, this option should be used only if congestion is expected to be a problem because it requires more runtime and causes area utilization to be less uniform across the available placement area. If congestion is found to be a problem after placement and optimization, it can be improved incrementally with the refine_placement command. Timing, area, and congestion optimization can also be done incrementally with the psynopt command. 

The -area_recovery option of the place_opt command allows placement tool to recover chip area where there is extra timing slack available. For example, it can resize cells smaller in timing paths where there is a positive timing slack. Placement is typically done before clock tree synthesis, so the clock network is ideal and does not have a clock buffer tree available for accurate clock network timing analysis. To get more accurate timing results, you should use the same commands as those used in synthesis tool to specify non-zero latency, uncertainty, and transition times for the clock network.



References:

1.Synopsys ICC Manual

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