Wednesday, 21 August 2013

Basic Terminology in Physical Design


Design: A circuit that performs one or more logical functions.

Cell: An instance of a design or library primitive within a design.

Port: The input or output of a design.

Pin: The input or output of a cell.

Net: A wire that connects ports to ports or ports to pins.

Clock: A timing reference object to describe a waveform for timing analysis.

Logical Libraries: Logical libraries are libraries which provide


  • Timing and functionality information for all standard cells (like AND, OR, Flipflops)
  • Timing information for Hard Macros (IP, ROM, RAM)
  • Define drive/load design rules ( Max Transition, Max Fanout, Max/Min Capacitance)   
Physical Libraries: Physical libraries are libraries which contain
  • Physical Information of Standard cells and Macro cells necessary for placement
  • Define placement unit tile 
Standard Cell: A standard cell is a group of transistors and interconnect structures that provides a boolean logic function (e.g., ANDORXORXNOR, inverters) or a storage function (flipflop or latch). 

Macro: Macros are intellectual properties that can be directly used in the design. These are need not to be design. For example memories, processor core, PLL etc. A macro can be hard or Soft macro.


Target Library: A technology library that Design Compiler maps to during optimization. Along with the link_library and search_path variables, you need to specify the logical library that will be used for mapping/optimization.

Link Library : The technology library that contains the definition of the cells used in the mapped
design. In principle should be the same as target_library unless a technology translation is being performed.

Search Path: If the library variables only specify file names, search_path is used to locate libraries. By default points to current working directory. By default, you must specify the unix-path for all files (relative or absolute). It specifies where to look for files.

Constraints: Constraints are the instructions that the designer can apply during various steps in the VLSI chip implementation, such as logic synthesis, Clock Tree synthesis (CTS), Place & Route, and Static Timing Analysis (STA).
Constraints are 2 types
  1. Design Rule Constraints
  2. Optimization Constraints  
Design Rule Constraints:
  • These are implicit constraints.
  •  The technology library (.lib) defines them. 
  • These constraints are requirements for a design to them. 
  • These constraints are requirements for a design to function correctly, and they apply to any design using the library. 
  • You can make these constraints more restrictive than optimization constraints.
Different types of Design Rule Constraints are
  1. Maximum Transition time
  2. Maximum Fanout
  3. Maximum/Minimum Capacitance
  4. Cell Degradation
Optimization Constraints:
  • These are explicit constraints; 
  • Designer define them. 
  • Optimization constraints apply to the design on which you are working for the duration of the dc_shell session and represent the design’s goals. 
  • They must be realistic.
  • Optimization Constraints describe the design goals (Area, Timing etc)
Maximum Transition time:
The maximum transition time for a net is the longest time required for its driving pin to change logic values. Typically fixed by buffering the output of driving gate. 

Maximum Fanout:
The maximum fanout of an output measures it's load driving capability. Most technology libraries (.lib) place fanout restrictions on driving pins, creating an implicit fanout constraint for every driving pin in designs using that library. Design Compiler models fanout restrictions by associating a fanout_load attribute with each input pin and a max_fanout attribute with each output (driving) pin on a cell.

Maximum Capacitance:
The maximum total capacitance that an output pin can drive. The maximum capacitance design rule constraint allows you to control the capacitance of nets  directly. (The design rule constraints max_fanout and max_transition limit the actual capacitance of nets indirectly.)

Minimum Capacitance:
The min_capacitance design rule specifies the minimum load a cell can drive. It specifies the lower bound of the range of loads with which a cell has been characterized to operate.

Optimization Constraints:

Timing Constraints:
Timing Constraints are required to communicate the design’s timing intentions to IC Compiler. They should be the same ones used for synthesis with Design Compiler (preferably SDC).

Synopsys Design Constraints (SDC):
A format used to specify the design intent including the timing, power and area constraints of a design. SDC is tool based. SDC contains 4 types of information.
  1. SDC Version
  2. SDC units
  3. Design Constraints
  4. comments
SDC version:
It sets the the version. Default version is 1.9

SDC units:
It specifies the units for capacitance, resistance, time, voltage, current and power.

Design Constraints:
The following are the design constraints are specified in SDC
                 1. system clock definition
                 2. clock delays
                 3. Multi Cycle Paths
                 4. Input & output delays
                 5. Minimum & Maximum path delays
                 6. Input transition and output load capacitance
                 7. False paths

Clock Tree Synthesis (CTS):
CTS is the process of inserting buffers/inverters along the clock paths of the design in order to balance the skew and to minimize insertion delay.
Skew: Skew is the difference in arrival of clock at two consecutive pins of a sequential element.

Positive skew- If capture clock comes late than launch clock then it is called positive skew.


Negative skew-If capture clock comes early than launch clock it is called –ve skew.
Local skew- It is the difference in arrival of clock at two consecutive pins of a sequential element.
Global skew- It is Defined as the difference between max insertion delay and the min insertion delay of any flops.
Boundary skew-It is defined as the difference between max insertion delay and the min insertion delay of boundary flops.
Useful skew-If clock is skewed intentionally to resolve violations, it is called useful skew.
Latency- Latency is the delay of the clock source and clock network delay.
Source latency- The delay from the clock origin point to the clock definition point in the design.
Network latency- The delay from the clock definition point to the clock pin of the register.
Uncertainity- Clock uncertainty is the time difference between the arrivals of clock signals at registers in one clock domain or between domains.
Jitter- Jitter is the short-term variations of a signal with respect to its ideal position in time. It is the variation of the clock period from edge to edge.

Setting Operating conditions:

1. Process Variation:
Variations in the process parameters, such as impurity concentration densities, oxide thicknesses, and diffusion depths. These are caused by non-uniform conditions during the deposition and/or the diffusion of the impurities. This introduces variations in the sheet resistances and transistor parameters such as the threshold voltage Variations in the dimensions of the devices, mainly resulting from the limited resolution of the photo lithographic process. This causes (W/L) variations in MOS transistors and mismatches in the emitter areas of bipolar devices.
2. Supply Voltage Variation
3. Ambient temperature Variations
4. It is important to analyze the design for best case and worst case scenarios. Best case to find issues with hold time violations and worst case to find issues with setup violations.

Timing Analysis:
Timing analysis is a method of validating the timing performance of a design  by checking the timing paths for timing violations. 

Net Delay: Interconnect relationships between a driver pin and its fanout
In the absence of physical design information, the timing analyser in Synopsys uses statistically generated wire load models to estimate wire lengths in a design. Two important concepts behind wire load models are
1. Wire load models provide a fanout to length relationship. So by knowing fanout, one can estimate the            length.
2. capacitance and resistance per unit length are given and the estimated length is then translated into                 estimated R and C values to give an estimated delays.
Wire load models are area dependent. Larger the area, greater the R and C value per unit length.

Cell Delay: 
  • Timing relationships between an input pin and an output pin, or between an output pin and another output pin of the same gate. 
  • Cell delay is calculated using non-linear delay models, which are stored in the ‘LM’ view of each cell. 
  • NLDM is highly accurate as it is derived from SPICE characterizations. 
  • The delay is a function of the input transition time of the cell (TInput) [also called slew], the driving strength of the cell (RCell), the wire capacitance (CNet) and the pin capacitance of the receivers (CPin). 
  • A slow input transition time will slow the rate at which the cell’s transistors can change state (from “on” to “off”), as well as a large output load (Cnet + Cpin), thereby increasing the “delay” of the logic gate. 

There is another NLDM table in the library to calculate output transition. Output transition of a cell becomes the input transition of the next cell down the chain.

CMOS Delay Model:  
   Transition Time = Drive R * Load C
   Cell Delay = f(Input Transition Time, Cnet + Cpin)
   Net Delay = f(Rnet, Cnet + Cpin)

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