Wednesday, 31 July 2013

Understanding of Setup and Hold Time violation using D-Flipflop


Understanding of Setup and Hold Time violation:

As discussed in earlier posts, Setup Time is the amount of time before the clock edge that the input signal needs to stable to guarantee it is properly accepted on the clock edge. If the data input is not constant the output of sequential element (FF) goes unpredictable state. The data can't propagated properly. So there is violation in the design. This violation is called as setup time violation.

To understand above statement, first we should know the basic operation of D-Flipflop. It is also known as a data or delay flip-flop. D-Flipflop is as shown in below figure 1.

                                                Figure 1. Positive Edge Triggered D-Flioflop
D-Flipflop is sequential element that propagates the data input (D) as output(Q) at the clock edge (i.e Posedge or Negedge). If the data input is propogated during posedge (i.e. 0 to 1), It is called as positive edge triggered flipflop. If the data input is propogated during negedge (i.e. 1 to 0), It is called as negative edge triggered flipflop.

                                               Figure 2. Positive Edge Triggered D-Flipflop  
As shown in above figure 2,  during the positive edge clock, the data input (D) is propogated as output (Q). 
That means, Even-though there is data input (D) is at input side, It can be propogated during clock event only. Assume if there is no clock event the output will be in the same state (i.e. Input is not propogated as output(Q)). one more thing we have to observe is the data input (D) is constant for certain amount of time before the clock edge (Posedge). So at every clock edge is the data input (D) is propogated as output(Q).

Case (1): If the Data Input (D) is not Constant



As shown in above figure, During the clock edge, the data input (D) is also moving from low level to high level that means the data (D) is not constant during clockedge. According to the basic operation of D-Flipflop, During the clock edge, the input should be propagate as output. In this case, during the clock edge the  D is moving from 0 to 1, So the output should be  0 to 1 (It's not the exact input Data) until the next clock edge. The flipflop is not working properly and the output of the D-Flipflop is (It is niether 0 nor 1) unpredictable, Until and unless the Data Input (D) is constant for certain amount of time before and after clockedge. The amount time the data input (D) should be constant before the clockedge is called as Setup Time   and the amount of time D should be constant after the clock edge is called as Hold Time. Violating these setup and hold time requirements is called as Setup and Hold time violations.



1 comment:

  1. I believe Fig. 2 is a negative edge triggered flip flop and not a posedge as stated. =p

    ReplyDelete