Thursday, 11 July 2013

Physical Design Flow

Physical Design Flow:



The design flow of the physical implementation is mentioned above in the figure. The physical design stage of the design flow is also known as the “place and route” stage. This is based upon the idea of physically placing the circuits, which form logic gates and represent a particular design, in such a way that the circuits can be fabricated. The typical physical design flow starts with a deciding the floor plan of a design, placement of standard cells, creating the clock tree for clock signal, routing the clock and signal nets. 

There are three main inputs to the physical implementation flow:
 1)Gate Level Netlist - It can be in the form of Verilog or VHDL. This netlist is produced during logical synthesis, which takes place prior to the physical design stage
• 2)Reference Library and Technology file - This is a collection of logic functions such as OR, AND, XOR, etc. The representation in the library is that of the physical shapes that will be fabricated. Technology files define the metal and via information related to particular technology.

• 3)Design Constraints – Design constraints (like system clock definition and clock delays, Multiple cycle paths, Input and output delays, Minimum and maximum path delays, Input transition and output load capacitance, False paths) are identical to those which were used during the front-end logic synthesis stage prior to physical design 
Setup Environment:
Before a design can be placed and routed, the environment for the design needs to be created. The goal of the design setup stage in the physical design flow is to prepare the design for floor planning. The first step is to create a design library. Without a design library, the physical design process using will not work. This library contains all of the logical and physical data that will need. Therefore the design library is also referenced as the design container during physical design. One of the inputs to the design library which will make the library technology specific is the technology file. 
Floorplanning :
Floor planning refers to the process of estimating the layout of the design. It includes the estimating the die size of a design, creating a placement rows for standard cells, placement of I/Os around the core boundary. Also macros are placed at floorplan stage. In broader sense pad info, power planning and macro placement together is known as floor planning. Apart from this aspect ratio of the core, utilization of the core area, cell orientation and core to I/O clearance are also be taken care during the floor plan stage. 
Power Planning :
Power planning is a step which typically is done with floor planning in which power grid network is created to distribute power to each part of the design equally. Power planning can be done manually as well as automatically through the tool. The power and ground rings are create around the core boundary with higher metal layers. The power and ground vertical and horizontal straps are also created to distribute power inside the core area i.e. to macros and standard cells. Finally the macro and stand cells pin connections are done to the straps and power and ground rails respectively. 
Placement:
Placement refers to the process of finalizing the exact location and orientation of each leaf instance in the design.A very important step in physical design cycle. A poor placement requires larger area and also results in performance degradation. It is the process of arranging a set of modules (std cells) on the layout surface. Each module has fixed shape and fixed terminal locations. A subset of modules may have pre-assigned positions (e.g., I/O pads). Standard cells are placed in the rows which are created during floorplaning stage.
Clock Tree Synthesis:
Clock Tree Synthesis (CTS) is a process of distributing clock signals in the design equally. The main goal of CTS is to meet design rule constraints, skew and insertion delay. CTS is the process of insertion of buffers or inverters along the clock paths of design in order to achieve zero/minimum skew or balanced skew.  Apart from these, useful skew is also added in the design by means of buffers and inverters.
Routing:
Routing refers to the process of physically connecting the instances in your design. 
There are four steps of routing operations:

1. Global routing
2. Track assignment
3. Detail routing
4. Search and repair  

Global Route assigns nets to specific metal layers and global routing cells. Global route tries to avoid congested global cells while minimizing detours. Global route also avoids pre-routed P/G, placement blockages and routing blockages.
Track Assignment (TA) assigns each net to a specific track and actual metal traces are laid down by it. It tries to make long, straight traces to avoid the number of vias. DRC is not followed in TA stage. TA operates on the entire design at once.
Detail Routing tries to fix all DRC violations after track assignment using a fixed size small area known as “SBox”. Detail route traverses the whole design box by box until entire routing pass is complete.
Search and Repair fixes remaining DRC violations through multiple iterative loops using progressively larger SBox sizes

 
Physical Verification:

Physical verification includes DRC and LVS checks. Design rule checks verify that the design meets the process design rules. Layout-versus-schematic checks compare the logical netlist with the layout database.

Sign-off is a final process of verifying the design for timing and power. 
References:
1. Synopsys IC Compiler Manual

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