Wednesday, 31 July 2013

Understanding of Setup and Hold Time violation using D-Flipflop


Understanding of Setup and Hold Time violation:

As discussed in earlier posts, Setup Time is the amount of time before the clock edge that the input signal needs to stable to guarantee it is properly accepted on the clock edge. If the data input is not constant the output of sequential element (FF) goes unpredictable state. The data can't propagated properly. So there is violation in the design. This violation is called as setup time violation.

To understand above statement, first we should know the basic operation of D-Flipflop. It is also known as a data or delay flip-flop. D-Flipflop is as shown in below figure 1.

                                                Figure 1. Positive Edge Triggered D-Flioflop
D-Flipflop is sequential element that propagates the data input (D) as output(Q) at the clock edge (i.e Posedge or Negedge). If the data input is propogated during posedge (i.e. 0 to 1), It is called as positive edge triggered flipflop. If the data input is propogated during negedge (i.e. 1 to 0), It is called as negative edge triggered flipflop.

                                               Figure 2. Positive Edge Triggered D-Flipflop  
As shown in above figure 2,  during the positive edge clock, the data input (D) is propogated as output (Q). 
That means, Even-though there is data input (D) is at input side, It can be propogated during clock event only. Assume if there is no clock event the output will be in the same state (i.e. Input is not propogated as output(Q)). one more thing we have to observe is the data input (D) is constant for certain amount of time before the clock edge (Posedge). So at every clock edge is the data input (D) is propogated as output(Q).

Case (1): If the Data Input (D) is not Constant



As shown in above figure, During the clock edge, the data input (D) is also moving from low level to high level that means the data (D) is not constant during clockedge. According to the basic operation of D-Flipflop, During the clock edge, the input should be propagate as output. In this case, during the clock edge the  D is moving from 0 to 1, So the output should be  0 to 1 (It's not the exact input Data) until the next clock edge. The flipflop is not working properly and the output of the D-Flipflop is (It is niether 0 nor 1) unpredictable, Until and unless the Data Input (D) is constant for certain amount of time before and after clockedge. The amount time the data input (D) should be constant before the clockedge is called as Setup Time   and the amount of time D should be constant after the clock edge is called as Hold Time. Violating these setup and hold time requirements is called as Setup and Hold time violations.



Wednesday, 24 July 2013

Macro Placement

Macro Placement:

Macros placement is done manually based on the connectivity with other macros and also with I/O pads. Flylines are used for placing macros manually. Fly/flight lines are virtual connections between macros and also macros to I/O pads. This helps the designer to get an idea about the logical connections between macros and pads. Fly/flight lines act as guidelines to the designer to reduce the routing resources to be used.

Based on these connections macros and I/O Pads/pins, Flylines are 3 types

1. Macro to Macro flylines.
2. Macro to I/O flylines.
3. Pin to Pin flylines.

1. Macro to Macro flylines:


                                          Figure(1): Macro to Macro flylines
As shown in above figure(1), When two macros are selected for macro to macro flylines, The total number of connections between them are shown. This gives an idea to the designer about which two macros to be placed closer. Hence, The two macros are placed closer to each other as shown in above figure (1) (Right side)

2. Macro to I/O flylines:


                                                 Figure(2): Macro to I/O flylines

As shown in above figure(2), when macro to I/O port Pin flylines are selected, the total number connections between macro and IO pins are shown. This gives an idea to the designer to identify the macros to be kept at the corners of the die or block. Hence the macro is placed closer to the periphery.

3. Pin to Pin flylines:

If two macros are selected for pin to pin fly lines, the virtual connections are shown and the much preciously connection to exact pin to pin will be shown. This guides the designer to choose an appropriate cell orientation (figure(3)) for the macros and as a resultant will be efficient routing.

                                              Figure 3(a): Pin to Pin flylines
                                   Figure 3(b): Cell Orientation (MY 90) based on Pin to Pin flylines



Static Timing Analysis (STA) Overview

Timing Analysis: 
Timing Analysis is a method of validating the timing performance of a design. i.e.  How fast the design is going to operate.

 Timing Analysis can be done in 2 ways

1. Static Timing Analysis (STA)
2. Dynamic Timing Analysis (DTA)

STA:

Static timing analysis is a method of validating the timing performance of a design by checking all possible paths for timing violations. PrimeTime(PT) checks for these violations.


To check a design for violations, STA tool breaks the design down into a set of timing paths, calculates the signal propagation delay along each path, and checks for violations of timing constraints inside the design and at the input/output interface.

DTA:


Another way to perform timing analysis is to use Dynamic Timing Analysis (DTA). It checks the functionality of design as well as timing. Dynamic simulation determines the full behavior of the circuit for a given set of input stimulus vectors. Compared with dynamic simulation, static timing analysis is much faster because it is not necessary to simulate the logical operation of the circuit.

Why STA is preferred over the DTA?


DTA requires a set of input stimulus vectors to check the timing characteristics of all paths in the design. So DTA makes the timing analysis very slow (Time taken for analyzing the design is very high because of the generation of test vectors for functionality check) when compared with STA. STA is faster than DTA beacuse there is no need to generate any kind of test vectors during STA. Static Timing Analysis is much faster because it is not necessary to simulate the logical operation of the circuit. That's why, STA is most popular way of doing timing analysis.

Timing Violations:

STA tool determines the timing paths and calculates the path delays, it can check for violations of timing constraints, such as setup and hold constraints.

Setup Constraint:
A setup constraint specifies how much time is necessary for data to be available at the input of a sequential device before the clock edge that captures the data in the device. This constraint enforces a maximum delay on the data path relative to the clock path.

Hold Constraint:
A hold constraint specifies how much time is necessary for data to be stable at the input of a sequential device after the clock edge that captures the data in the device. This constraint enforces a minimum delay on the data path relative to the clock path.

In addition to setup and hold constraints, PrimeTime can also check recovery/removal constraints, data-to-data constraints, clock-gating setup/hold constraints, and minimum pulse width for clock signals.

Slack:
The amount of time by which a violation is avoided is called the slack. For example, for a setup constraint, if a signal must reach a cell input at no later than 10 ns and is determined to arrive at 6 ns, the slack is 4 ns. A slack of 0 means that the constraint is just barely satisfied.
A negative slack indicates a timing violation.

    Slack = Required Arrival Time - Actual Arrival Time


If Slack = 0, The design is critically working at the desired frequency
If Slack >0, The design is meeting the timing requirements and still it can be improved
If Slack<0,  The design is not meeting the timing constraints, It has timing violations to be fixed.

Timing Violations:

1. Setup Time violation
2. Hold Time violation

Setup Time Violation:

Setup time is the amount of time before the clock edge that the input signal needs to stable to guarantee it is properly accepted on the clock edge. If the data input is not constant the output of sequential element (FF) goes unpredictable state. The data can't propagated properly. So there is violation in the design. This violation is called as setup time violation.

Hold Time Violation:

Hold time is the amount of time after the clock edge that the input  should be stable to guarantee it is properly accepted on the clock edge. If the data input is not constant the output of sequential element (FF) goes unpredictable state. The data  (D) can't propagated properly. So there is violation in the design. This violation is called as Hold time violation.






Reference:
1. Synopsys Primetime Manual

Wednesday, 17 July 2013

Floorplan Control Parameters

The following are the Control Parameters during Floorplan

1. Aspect Ratio:

  • Core Utilization
  • Aspect ratio (H/W)
  • Row/Core ratio

2.Width and Height:

  • Width
  • Height
  • Row/Core ratio



1. Aspect Ratio (Ar):
 Aspect ratio is the ratio between vertical routing resources to horizontal routing resources. If you specify a ratio of 1.00, the height and width are the same and therefore the core is a square. If you specify a ratio of 3.00, the height is three times the width.

                             Aspect Ratio(Ar) = Horizontal routing resource (H)/Vertical routing resource (V)

  • Core Utilization (Cu): It indicates the amount of core area used for cell placement. The number is calculated as a ratio of the total cell area (for hard macros and standard cells or soft macro cells) to the core area. A core utilization of 0.8, for example, means that 80% of the core area is used for cell placement and 20 percent is available for routing.
            Core Utilization(Cu) = Standard Cell area/(Row area + Channel area)

  • Row to Core Ratio (Rcr): It indicates the amount of channel space to provide for routing between the cell rows. The smaller the number, the more space is left for routing. A value of 1.0 leaves no routing channel space.
          Rcr = Row area / Core area (H x V)


  • Total utilization T(F) of floorplan F is derived using the following equation: 
                  
                                T(F) = (A(m) + A(p) + A(s) ) / A
                    
                                     where A(m) = Area occupied by macros
                                                A(p) = Area occupied by Pads/ Pad fillers
                                                A(s) = Area occupied by Standard Cells
  • Cell row utilization C(F) of floorplan F is approximated using the following equation:
             
                          C(F) = A(s) / A(R –union(B, E, m, p))
                               Where R= All cell rows
                                           B= All placement blockages
                                           E= Exclusive Regions


Friday, 12 July 2013

Floorplanning

Floorplanning:

Floorplanning includes macro/block placement, pin placement, power planning, and power grid design. What makes the job more important is that the decisions taken for macro/block placement,  I/O-pad placement, and power planning directly or indirectly impact the overall implementation cycle.

Lots of iterations happen to get an optimum floorplan. The designer takes care of the design parameters, such as power, area, timing, and performance during floorplanning. These estimations are repeatedly reviewed, based on the feedback of other stakeholders such as the implementation team, IP owners, and RTL designers. The outcome of floorplanning is a proper arrangement of macros/blocks, power grid, pin placement, and partitioned blocks that can be implemented in parallel.


The first rule of thumb for floorplanning is to arrange the hard macros and memories in such a manner that you end up with a core area square in shape. This is always not possible, however, because of the large number of analog-IP blocks, memories, and various other requirements in design.

The following are decided at the floorplanning stage
  1.    Die size, core size of the chip 
  2.  Macro placement
  3.  I/O pad’s location
  4.   Plan for power
  5.   Row configuration     
      In simple words, power planning and macro placement together is known as floor planning. Apart from this aspect ratio of the core, utilization of the core area, cell orientation and core to I/O clearance are also be taken care during the floor plan stage. we will discuss about these in our next blog.
    Inputs for Floorplanning:    
  •        Synthesized Netlist (.v or .vhdl)
  •        Design Constraints (SDC)
  •        IO Constraints
  •       Floorplan Control Parameters
  •      Technology File 
  •       TLU+ Model

Thursday, 11 July 2013

Physical Design Flow

Physical Design Flow:



The design flow of the physical implementation is mentioned above in the figure. The physical design stage of the design flow is also known as the “place and route” stage. This is based upon the idea of physically placing the circuits, which form logic gates and represent a particular design, in such a way that the circuits can be fabricated. The typical physical design flow starts with a deciding the floor plan of a design, placement of standard cells, creating the clock tree for clock signal, routing the clock and signal nets. 

There are three main inputs to the physical implementation flow:
 1)Gate Level Netlist - It can be in the form of Verilog or VHDL. This netlist is produced during logical synthesis, which takes place prior to the physical design stage
• 2)Reference Library and Technology file - This is a collection of logic functions such as OR, AND, XOR, etc. The representation in the library is that of the physical shapes that will be fabricated. Technology files define the metal and via information related to particular technology.

• 3)Design Constraints – Design constraints (like system clock definition and clock delays, Multiple cycle paths, Input and output delays, Minimum and maximum path delays, Input transition and output load capacitance, False paths) are identical to those which were used during the front-end logic synthesis stage prior to physical design 
Setup Environment:
Before a design can be placed and routed, the environment for the design needs to be created. The goal of the design setup stage in the physical design flow is to prepare the design for floor planning. The first step is to create a design library. Without a design library, the physical design process using will not work. This library contains all of the logical and physical data that will need. Therefore the design library is also referenced as the design container during physical design. One of the inputs to the design library which will make the library technology specific is the technology file. 
Floorplanning :
Floor planning refers to the process of estimating the layout of the design. It includes the estimating the die size of a design, creating a placement rows for standard cells, placement of I/Os around the core boundary. Also macros are placed at floorplan stage. In broader sense pad info, power planning and macro placement together is known as floor planning. Apart from this aspect ratio of the core, utilization of the core area, cell orientation and core to I/O clearance are also be taken care during the floor plan stage. 
Power Planning :
Power planning is a step which typically is done with floor planning in which power grid network is created to distribute power to each part of the design equally. Power planning can be done manually as well as automatically through the tool. The power and ground rings are create around the core boundary with higher metal layers. The power and ground vertical and horizontal straps are also created to distribute power inside the core area i.e. to macros and standard cells. Finally the macro and stand cells pin connections are done to the straps and power and ground rails respectively. 
Placement:
Placement refers to the process of finalizing the exact location and orientation of each leaf instance in the design.A very important step in physical design cycle. A poor placement requires larger area and also results in performance degradation. It is the process of arranging a set of modules (std cells) on the layout surface. Each module has fixed shape and fixed terminal locations. A subset of modules may have pre-assigned positions (e.g., I/O pads). Standard cells are placed in the rows which are created during floorplaning stage.
Clock Tree Synthesis:
Clock Tree Synthesis (CTS) is a process of distributing clock signals in the design equally. The main goal of CTS is to meet design rule constraints, skew and insertion delay. CTS is the process of insertion of buffers or inverters along the clock paths of design in order to achieve zero/minimum skew or balanced skew.  Apart from these, useful skew is also added in the design by means of buffers and inverters.
Routing:
Routing refers to the process of physically connecting the instances in your design. 
There are four steps of routing operations:

1. Global routing
2. Track assignment
3. Detail routing
4. Search and repair  

Global Route assigns nets to specific metal layers and global routing cells. Global route tries to avoid congested global cells while minimizing detours. Global route also avoids pre-routed P/G, placement blockages and routing blockages.
Track Assignment (TA) assigns each net to a specific track and actual metal traces are laid down by it. It tries to make long, straight traces to avoid the number of vias. DRC is not followed in TA stage. TA operates on the entire design at once.
Detail Routing tries to fix all DRC violations after track assignment using a fixed size small area known as “SBox”. Detail route traverses the whole design box by box until entire routing pass is complete.
Search and Repair fixes remaining DRC violations through multiple iterative loops using progressively larger SBox sizes

 
Physical Verification:

Physical verification includes DRC and LVS checks. Design rule checks verify that the design meets the process design rules. Layout-versus-schematic checks compare the logical netlist with the layout database.

Sign-off is a final process of verifying the design for timing and power. 
References:
1. Synopsys IC Compiler Manual